Hi Dirk,
Thanks i got some useful information.
Warm Regards,
Akshay
--- On Thu, 10/9/09, Dirk Behme wrote:
> From: Dirk Behme
> Subject: Re: [U-Boot] Why Cache flush required in some ARM Cortex boards to
> enable D cache?
> To: "akshay ts"
> Cc: u-boot@lists.den
akshay ts wrote:
> Hi,
> I ran into problems when i enabled D cache. But later i found out that cache
> flush was required before enabling D Cache.
Flush or invalidate? See below...
> What i dont understand is why is it required?. Since earlier D cache is never
> enabled and so nothing should
Hi,
I ran into problems when i enabled D cache. But later i found out that cache
flush was required before enabling D Cache. What i dont understand is why is it
required?. Since earlier D cache is never enabled and so nothing should be
present in the cache.
Flushing is only required during cont
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