RE: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver
Hi Cédric, > -Original Message- > From: Cédric Le Goater > Sent: Friday, July 8, 2022 4:52 PM > To: Chin-Ting Kuo ; Joel Stanley > > Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver > > On 7/8/22 07:42, Chin-Ting Kuo wrote: > > Hi Joel, > > > >> -Original Message- > >> From: Joel Stanley > >> Sent: Thursday, July 7, 2022 1:37 PM > >> Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver > >> > >> Hi Chin-Ting, > >> > >> On Tue, 24 May 2022 at 05:58, Chin-Ting Kuo > >> wrote: > >>> > >>> Add ASPEED BMC FMC/SPI memory controller driver with spi-mem > >>> interface for AST2500 and AST2600 platform. > >> > >> Have you considered including 2400 support in your patch set? > >> > > > > No. But in order to achieve sustainability and completeness, we will add > AST2400 part in the next patch version. > > Could you please provide the AST2400 support as a separate patch on top of > the AST2500/AST2600 ? It helps to understand the differences. > Okay, it will be more clear. Best Wishes, Chin-Ting > Thanks, > > C.
Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver
On 7/8/22 07:42, Chin-Ting Kuo wrote: Hi Joel, -Original Message- From: Joel Stanley Sent: Thursday, July 7, 2022 1:37 PM Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver Hi Chin-Ting, On Tue, 24 May 2022 at 05:58, Chin-Ting Kuo wrote: Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. Have you considered including 2400 support in your patch set? No. But in order to achieve sustainability and completeness, we will add AST2400 part in the next patch version. Could you please provide the AST2400 support as a separate patch on top of the AST2500/AST2600 ? It helps to understand the differences. Thanks, C.
RE: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver
Hi Joel, > -Original Message- > From: Joel Stanley > Sent: Thursday, July 7, 2022 1:37 PM > Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver > > Hi Chin-Ting, > > On Tue, 24 May 2022 at 05:58, Chin-Ting Kuo > wrote: > > > > Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface > > for AST2500 and AST2600 platform. > > Have you considered including 2400 support in your patch set? > No. But in order to achieve sustainability and completeness, we will add AST2400 part in the next patch version. Best Wishes, Chin-Ting > I have prepared a series that adds upstream support for the 2400. We already > have support in other drivers (gpio, i2c, sdhci, timer, wdt) so there's no > blocker > in including support in your patch. > > Cheers, > > Joel > > > > > There are three SPI memory controllers embedded in an ASPEED SoC. > > - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM > >fetches initial device boot image from FMC chip select(CS) 0. > > > > - SPI1: Play the role of a SPI Master controller. Or, there is a > > dedicated path for HOST(X86) to access its BIOS flash mounted > > under BMC. spi-aspeed.c implements the control sequence when > > SPI1 is a SPI master. > > > > - SPI2: It is a pure SPI flash controller. For most scenarios, flashes > > mounted under it are for pure storage purpose. > > > > ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. > > Three types of command mode are supported, normal mode, command > > read/write mode and user mode. > > - Normal mode: Default mode. After power on, normal read command 03h > or > >13h is used to fetch boot image from SPI flash. > >- AST2500: Only 03h command can be used after power > on > > or reset. > >- AST2600: If FMC04[6:4] is set, 13h command is used, > > otherwise, 03h command. > >The address length is decided by FMC04[2:0]. > > > > - Command mode: SPI controller can send command and address > > automatically when CPU read/write the related > remapped > > or decoded address area. The command used by this > mode > > can be configured by FMC10/14/18[23:16]. Also, the > > address length is decided by FMC04[2:0]. This mode will > > be implemented in the following patch series. > > > > - User mode: It is a traditional and pure SPI operation, where > > SPI transmission is controlled by CPU. It is the main > > mode in this patch. > > > > Each SPI controller in ASPEED SoC has its own decoded address mapping. > > Within each SPI controller decoded address, driver can assign a > > specific address region for each CS of a SPI controller. The decoded > > address cannot overlap to each other. With normal mode and command > > mode, the decoded address accessed by the CPU determines which CS is > active. > > When user mode is adopted, the CS decoded address is a FIFO, CPU can > > send/receive any SPI transmission by accessing the related decoded > > address for the target CS. > > > > Signed-off-by: Chin-Ting Kuo > > --- > > v2: Remove defconfig files from this patch. > > > > drivers/spi/Kconfig | 8 + > > drivers/spi/Makefile | 1 + > > drivers/spi/spi-aspeed.c | 822 > > +++ > > 3 files changed, 831 insertions(+) > > create mode 100644 drivers/spi/spi-aspeed.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > > a1e515cb2b..a616294910 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -387,6 +387,14 @@ config SANDBOX_SPI > > }; > > }; > > > > +config SPI_ASPEED > > + bool "ASPEED SPI controller driver" > > + depends on DM_SPI && SPI_MEM > > + default n > > + help > > + Enable ASPEED SPI controller driver for AST2500 > > + and AST2600 SoCs. > > + > > config SPI_SIFIVE > > bool "SiFive SPI driver" > > help > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > > 06e81b465b..36a4bd5dce 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -9,6 +9,7 @@ obj-y += spi-uclass.o > > obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cad
Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver
Hi Chin-Ting, On Tue, 24 May 2022 at 05:58, Chin-Ting Kuo wrote: > > Add ASPEED BMC FMC/SPI memory controller driver with > spi-mem interface for AST2500 and AST2600 platform. Have you considered including 2400 support in your patch set? I have prepared a series that adds upstream support for the 2400. We already have support in other drivers (gpio, i2c, sdhci, timer, wdt) so there's no blocker in including support in your patch. Cheers, Joel > > There are three SPI memory controllers embedded in an ASPEED SoC. > - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM >fetches initial device boot image from FMC chip select(CS) 0. > > - SPI1: Play the role of a SPI Master controller. Or, there is a > dedicated path for HOST(X86) to access its BIOS flash mounted > under BMC. spi-aspeed.c implements the control sequence when > SPI1 is a SPI master. > > - SPI2: It is a pure SPI flash controller. For most scenarios, flashes > mounted under it are for pure storage purpose. > > ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. > Three types of command mode are supported, normal mode, command > read/write mode and user mode. > - Normal mode: Default mode. After power on, normal read command 03h or >13h is used to fetch boot image from SPI flash. >- AST2500: Only 03h command can be used after power on > or reset. >- AST2600: If FMC04[6:4] is set, 13h command is used, > otherwise, 03h command. >The address length is decided by FMC04[2:0]. > > - Command mode: SPI controller can send command and address > automatically when CPU read/write the related remapped > or decoded address area. The command used by this mode > can be configured by FMC10/14/18[23:16]. Also, the > address length is decided by FMC04[2:0]. This mode will > be implemented in the following patch series. > > - User mode: It is a traditional and pure SPI operation, where > SPI transmission is controlled by CPU. It is the main > mode in this patch. > > Each SPI controller in ASPEED SoC has its own decoded address mapping. > Within each SPI controller decoded address, driver can assign a specific > address region for each CS of a SPI controller. The decoded address > cannot overlap to each other. With normal mode and command mode, the > decoded address accessed by the CPU determines which CS is active. > When user mode is adopted, the CS decoded address is a FIFO, CPU can > send/receive any SPI transmission by accessing the related decoded > address for the target CS. > > Signed-off-by: Chin-Ting Kuo > --- > v2: Remove defconfig files from this patch. > > drivers/spi/Kconfig | 8 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-aspeed.c | 822 +++ > 3 files changed, 831 insertions(+) > create mode 100644 drivers/spi/spi-aspeed.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index a1e515cb2b..a616294910 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -387,6 +387,14 @@ config SANDBOX_SPI > }; > }; > > +config SPI_ASPEED > + bool "ASPEED SPI controller driver" > + depends on DM_SPI && SPI_MEM > + default n > + help > + Enable ASPEED SPI controller driver for AST2500 > + and AST2600 SoCs. > + > config SPI_SIFIVE > bool "SiFive SPI driver" > help > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 06e81b465b..36a4bd5dce 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -9,6 +9,7 @@ obj-y += spi-uclass.o > obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o > obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o > obj-$(CONFIG_SOFT_SPI) += soft_spi.o > +obj-$(CONFIG_SPI_ASPEED) += spi-aspeed.o > obj-$(CONFIG_SPI_MEM) += spi-mem.o > obj-$(CONFIG_TI_QSPI) += ti_qspi.o > obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o > diff --git a/drivers/spi/spi-aspeed.c b/drivers/spi/spi-aspeed.c > new file mode 100644 > index 00..9574aff793 > --- /dev/null > +++ b/drivers/spi/spi-aspeed.c > @@ -0,0 +1,822 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * ASPEED FMC/SPI Controller driver > + * > + * Copyright (c) 2022 ASPEED Corporation. > + * Copyright (c) 2022 IBM Corporation. > + * > + * Author: > + * Chin-Ting Kuo > + * Cedric Le Goater > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* ASPEED FMC/SPI memory control register related */ > +#define REG_CE_TYPE_SETTING 0x00 > +#define REG_CE_ADDR_MODE_CTRL0x04 > +#define REG_INTR_CTRL_STATUS 0x08 > +#define REG_CE0_CTRL_REG
RE: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver
Hi Cédric, > -Original Message- > From: Cédric Le Goater > Sent: Monday, July 4, 2022 11:25 PM > Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver > > Hello Chin-Ting, > > On 7/3/22 10:47, Chin-Ting Kuo wrote: > > Hi Cédric, > > > > Thanks for the review. > > > >> -Original Message- > >> From: Cédric Le Goater > >> Sent: Friday, July 1, 2022 5:28 PM > >> To: Chin-Ting Kuo ; ChiaWei Wang > >> ; lu...@denx.de; sean...@gmail.com; > Ryan > >> Chen ; BMC-SW > ; > >> ja...@amarulasolutions.com; vigne...@ti.com; u-boot@lists.denx.de; > >> p.ya...@ti.com > >> Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver > >> > >> Hello Chin-Ting, > >> > >> On 5/24/22 07:56, Chin-Ting Kuo wrote: > >>> Add ASPEED BMC FMC/SPI memory controller driver with spi-mem > >>> interface for AST2500 and AST2600 platform. > >>> > >>> There are three SPI memory controllers embedded in an ASPEED SoC. > >>> - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM > >>> fetches initial device boot image from FMC chip select(CS) 0. > >>> > >>> - SPI1: Play the role of a SPI Master controller. Or, there is a > >>> dedicated path for HOST(X86) to access its BIOS flash > mounted > >>> under BMC. spi-aspeed.c implements the control sequence > when > >>> SPI1 is a SPI master. > >>> > >>> - SPI2: It is a pure SPI flash controller. For most scenarios, flashes > >>> mounted under it are for pure storage purpose. > >>> > >>> ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. > >>> Three types of command mode are supported, normal mode, command > >>> read/write mode and user mode. > >>> - Normal mode: Default mode. After power on, normal read command > 03h > >> or > >>> 13h is used to fetch boot image from SPI flash. > >>> - AST2500: Only 03h command can be used after > power > >> on > >>> or reset. > >>> - AST2600: If FMC04[6:4] is set, 13h command is > used, > >>> otherwise, 03h command. > >>> The address length is decided by FMC04[2:0]. > >>> > >>> - Command mode: SPI controller can send command and address > >>> automatically when CPU read/write the related > >> remapped > >>> or decoded address area. The command used by > this > >> mode > >>> can be configured by FMC10/14/18[23:16]. Also, > the > >>> address length is decided by FMC04[2:0]. This mode > >> will > >>> be implemented in the following patch series. > >>> > >>> - User mode: It is a traditional and pure SPI operation, where > >>>SPI transmission is controlled by CPU. It is the main > >>>mode in this patch. > >>> > >>> Each SPI controller in ASPEED SoC has its own decoded address mapping. > >>> Within each SPI controller decoded address, driver can assign a > >>> specific address region for each CS of a SPI controller. The decoded > >>> address cannot overlap to each other. With normal mode and command > >>> mode, the decoded address accessed by the CPU determines which CS is > >> active. > >>> When user mode is adopted, the CS decoded address is a FIFO, CPU can > >>> send/receive any SPI transmission by accessing the related decoded > >>> address for the target CS. > >>> > >>> Signed-off-by: Chin-Ting Kuo > >> > >> I would split the patch furthermore to ease reading. > > > > Okay, this will be update in the next version. > > > >>1 - Add basic support > >> > >>with default decoding ranges set for all possible CS, even > >>without a device. > >> > >>WE only have USER mode for now. So it's not important to > >>correctly set the ranges since we won't use them before > >>direct mapping is introduced. They should not overlap, > >>that's all. > >> > >>2 - decoding range adjustments > >> > >>On that topic
Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver
Hello Chin-Ting, On 7/3/22 10:47, Chin-Ting Kuo wrote: Hi Cédric, Thanks for the review. -Original Message- From: Cédric Le Goater Sent: Friday, July 1, 2022 5:28 PM To: Chin-Ting Kuo ; ChiaWei Wang ; lu...@denx.de; sean...@gmail.com; Ryan Chen ; BMC-SW ; ja...@amarulasolutions.com; vigne...@ti.com; u-boot@lists.denx.de; p.ya...@ti.com Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver Hello Chin-Ting, On 5/24/22 07:56, Chin-Ting Kuo wrote: Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. Signed-off-by: Chin-Ting Kuo I would split the patch furthermore to ease reading. Okay, this will be update in the next version. 1 - Add basic support with default decoding ranges set for all possible CS, even without a device. WE only have USER mode for now. So it's not important to correctly set the ranges since we won't use them before direct mapping is introduced. They should not overlap, that's all. 2 - decoding range adjustments On that topic, we might want to take the simple DT approach with a "ranges" property defining the mapping windows of each CE. I think it is safer than trying to compute perfect ranges like on Linux. 3 - clock settings That should simply be the property defined in the DT --- v2: Remove defconfig files from this patch. drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-aspeed.c | 822 +++ 3 files changed, 831 insertions(+) create mode 100644 drivers/spi/spi-aspeed.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2b..a616294910 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -387,6 +387,14 @@ config SANDBOX_SPI }; }; +config SPI_ASPEED + bool "ASPEED SPI controller driver" + depends on DM_SPI && SPI_MEM + default n + help + Enable ASPEED SPI controller driver for AST2500 + and AST2600 SoCs. + config SPI_SIFIVE bool "SiFive SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06e81b465b..36a4bd5dce 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -9,6 +9,7 @@ obj-y += spi-uclass.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o obj-$(CONFIG_SOFT_SPI) += soft_spi.o +obj-$(CONFIG_SPI_ASPEED) += spi-aspeed.o obj-$(CONFIG_SPI_MEM) += spi-mem.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o d
RE: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver
Hi Cédric, Thanks for the review. > -Original Message- > From: Cédric Le Goater > Sent: Friday, July 1, 2022 5:28 PM > To: Chin-Ting Kuo ; ChiaWei Wang > ; lu...@denx.de; sean...@gmail.com; > Ryan Chen ; BMC-SW > ; ja...@amarulasolutions.com; vigne...@ti.com; > u-boot@lists.denx.de; p.ya...@ti.com > Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver > > Hello Chin-Ting, > > On 5/24/22 07:56, Chin-Ting Kuo wrote: > > Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface > > for AST2500 and AST2600 platform. > > > > There are three SPI memory controllers embedded in an ASPEED SoC. > > - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM > > fetches initial device boot image from FMC chip select(CS) 0. > > > > - SPI1: Play the role of a SPI Master controller. Or, there is a > > dedicated path for HOST(X86) to access its BIOS flash mounted > > under BMC. spi-aspeed.c implements the control sequence when > > SPI1 is a SPI master. > > > > - SPI2: It is a pure SPI flash controller. For most scenarios, flashes > > mounted under it are for pure storage purpose. > > > > ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. > > Three types of command mode are supported, normal mode, command > > read/write mode and user mode. > > - Normal mode: Default mode. After power on, normal read command 03h > or > > 13h is used to fetch boot image from SPI flash. > > - AST2500: Only 03h command can be used after power > on > >or reset. > > - AST2600: If FMC04[6:4] is set, 13h command is used, > >otherwise, 03h command. > > The address length is decided by FMC04[2:0]. > > > > - Command mode: SPI controller can send command and address > > automatically when CPU read/write the related > remapped > > or decoded address area. The command used by this > mode > > can be configured by FMC10/14/18[23:16]. Also, the > > address length is decided by FMC04[2:0]. This mode > will > > be implemented in the following patch series. > > > > - User mode: It is a traditional and pure SPI operation, where > > SPI transmission is controlled by CPU. It is the main > > mode in this patch. > > > > Each SPI controller in ASPEED SoC has its own decoded address mapping. > > Within each SPI controller decoded address, driver can assign a > > specific address region for each CS of a SPI controller. The decoded > > address cannot overlap to each other. With normal mode and command > > mode, the decoded address accessed by the CPU determines which CS is > active. > > When user mode is adopted, the CS decoded address is a FIFO, CPU can > > send/receive any SPI transmission by accessing the related decoded > > address for the target CS. > > > > Signed-off-by: Chin-Ting Kuo > > I would split the patch furthermore to ease reading. Okay, this will be update in the next version. > 1 - Add basic support > > with default decoding ranges set for all possible CS, even > without a device. > > WE only have USER mode for now. So it's not important to > correctly set the ranges since we won't use them before > direct mapping is introduced. They should not overlap, > that's all. > > 2 - decoding range adjustments > > On that topic, we might want to take the simple DT approach > with a "ranges" property defining the mapping windows of each > CE. I think it is safer than trying to compute perfect ranges > like on Linux. > > 3 - clock settings > > That should simply be the property defined in the DT > > > > --- > > v2: Remove defconfig files from this patch. > > > > drivers/spi/Kconfig | 8 + > > drivers/spi/Makefile | 1 + > > drivers/spi/spi-aspeed.c | 822 > +++ > > 3 files changed, 831 insertions(+) > > create mode 100644 drivers/spi/spi-aspeed.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > > a1e515cb2b..a616294910 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -387,6 +387,14 @@ config SANDBOX_SPI > > }; > > }; > > > > +config SPI_ASPEED > > + bool "ASPEED SPI controller driver&qu
Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver
Hello Chin-Ting, On 5/24/22 07:56, Chin-Ting Kuo wrote: Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. Signed-off-by: Chin-Ting Kuo I would split the patch furthermore to ease reading. 1 - Add basic support with default decoding ranges set for all possible CS, even without a device. WE only have USER mode for now. So it's not important to correctly set the ranges since we won't use them before direct mapping is introduced. They should not overlap, that's all. 2 - decoding range adjustments On that topic, we might want to take the simple DT approach with a "ranges" property defining the mapping windows of each CE. I think it is safer than trying to compute perfect ranges like on Linux. 3 - clock settings That should simply be the property defined in the DT --- v2: Remove defconfig files from this patch. drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-aspeed.c | 822 +++ 3 files changed, 831 insertions(+) create mode 100644 drivers/spi/spi-aspeed.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2b..a616294910 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -387,6 +387,14 @@ config SANDBOX_SPI }; }; +config SPI_ASPEED + bool "ASPEED SPI controller driver" + depends on DM_SPI && SPI_MEM + default n + help + Enable ASPEED SPI controller driver for AST2500 + and AST2600 SoCs. + config SPI_SIFIVE bool "SiFive SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06e81b465b..36a4bd5dce 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -9,6 +9,7 @@ obj-y += spi-uclass.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o obj-$(CONFIG_SOFT_SPI) += soft_spi.o +obj-$(CONFIG_SPI_ASPEED) += spi-aspeed.o obj-$(CONFIG_SPI_MEM) += spi-mem.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o diff --git a/drivers/spi/spi-aspeed.c b/drivers/spi/spi-aspeed.c new file mode 100644 index 00..9574aff793 --- /dev/null +++ b/drivers/spi/spi-aspeed.c @@ -0,0 +1,822 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ASPEED FMC/SPI Controller driver + * + * Copyright (c) 2022 ASPEED Corporation. + * Copyright (c) 2022 IBM Corporation. + * + * Author: + * Chin-Ting Kuo + * Cedric Le Goater + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include
