Hello list!
First of all, sorry if I ask here the same question I asked in the ST
Community Forum, but I think for a u-boot (SPL) related question is
better to use this Mailing List.
I have to boot up a custom board based on STM32MP157D MPU with 1GB of
SDRAM (2x4 Gb 16bit chips) for a total of 32bit 8 Gigabit DDR3.
Basically more or less like the STMicroelectronics ED1 Board.
I am using a u-boot v2022.01-rc3 from the last months of the 2021.
I am using it because I have already built a custom board with
STM32MP151 MCU adapting some code / drivers / configuration and I do not
want to reinvent the wheel with another u-boot version.
I want to up-to-date u-boot to the latest version, and if possible, ask
for an inclusion update in the main tree of u-boot in the next release
window.
Anyway, I am stuck when loading from microSD the SPL and before
relocating u-boot to the 1Gig SDRAM space.
I have (as far as I know) enabled the lowlevel serial output to have
some stuff in the serial line (uart4) and I clearly see what's happen
until it hangs.
I used to have clk init code with a lot of debugging information, just
to see if the device-tree is configured correctly.
stm32mp1_clk rcc@50000000: hsi clock rate: 64000000Hz
stm32mp1_clk rcc@50000000: hse clock rate: 24000000Hz
stm32mp1_clk rcc@50000000: csi clock rate: 4000000Hz
stm32mp1_clk rcc@50000000: lsi clock rate: 32000Hz
stm32mp1_clk rcc@50000000: lse clock rate: 32768Hz
stm32mp1_clk rcc@50000000: No source clock "i2s_ckin"stm32mp1_clk rcc@50000000:
DT for PLL 0 with OPP
stm32mp1_clk rcc@50000000: DT for PLL 1 @ st,pll@1
stm32mp1_clk rcc@50000000: DT for PLL 2 @ st,pll@2
stm32mp1_clk rcc@50000000: DT for PLL 3 @ st,pll@3
stm32mp1_clk rcc@50000000: configuration MCO
stm32mp1_clk rcc@50000000: switch ON osillator
stm32mp1_clk rcc@50000000: come back to HSI
stm32mp1_clk rcc@50000000: pll stop
stm32mp1_clk rcc@50000000: configure HSIDIV
HSI_KER clock is the parent STGEN of clk id 128
id=6 clock = 3d09000 : 64000 kHz
stm32mp1_clk rcc@50000▒
From now, I think the UART controller is updated/modified to the
baudrate change and the stuff to write to serial console has some
garbage on screen...
▒▒▒▒▒f▒▒f▒▒▒▒▒
f
▒f3▒▒▒?`?▒▒▒▒f▒▒▒▒▒▒▒▒f▒
▒▒▒▒▒▒▒▒▒▒▒▒x<▒▒~<f??f<▒3xf▒▒▒▒▒▒f??<f<怘▒?`?▒▒▒▒f▒▒▒▒▒▒▒▒f▒
▒▒▒▒▒▒▒▒▒▒▒▒x<▒▒~<f??f<▒3xf▒▒f
▒▒▒f▒▒x
x▒▒▒f▒▒f▒▒▒▒▒▒▒▒f▒
▒▒▒▒▒▒▒▒▒▒▒▒x<▒▒~<f??f<▒3xf▒▒▒03`▒▒f▒▒x
x▒▒▒f▒▒f▒▒▒▒▒▒▒▒f▒
▒▒▒▒▒▒▒▒▒▒▒▒x<▒▒~<f??f<▒3xf▒▒▒▒03`▒▒f▒▒x
x▒▒▒f▒▒f▒▒▒▒▒▒▒▒f▒
▒▒▒▒▒▒▒▒▒▒▒▒x<▒▒~<f??f<▒3xf▒▒Ø03`▒▒f▒▒x
x▒▒▒f▒▒f▒▒▒▒▒▒▒▒f▒
▒▒▒▒▒▒▒▒▒▒▒▒x<▒▒~<f??f<▒3xf▒▒▒x▒▒▒▒f▒▒x
x▒▒▒f▒▒f▒▒▒▒▒▒▒▒f▒
▒▒▒▒▒▒▒▒▒▒f?`?▒f?`?▒3xf▒▒▒03`▒▒f▒▒x
x▒▒▒f▒▒f▒▒▒▒▒▒▒▒f▒
▒▒▒▒▒▒▒▒▒▒f?`?▒f?`?▒3xf▒▒▒▒03`▒▒f▒▒x
x▒▒▒f▒▒f▒▒▒▒▒▒▒▒f▒
▒▒▒▒▒▒▒▒▒▒f?`?▒f?`?▒3xf▒▒Ø03`▒▒f▒▒x
x▒▒▒f▒▒f▒▒▒▒▒▒▒▒f▒
▒▒▒▒▒▒▒▒▒▒f?`?▒f?`?▒3xf▒▒▒x▒▒?`?▒▒▒▒f▒▒▒▒▒▒▒▒f▒
Q▒EeKC▒▒▒JUc▒KT▒U▒▒▒▒▒▒▒▒▒▒5j▒jUԵ▒J▒,▒k▒
Rk▒$▒X▒Y▒▒*▒T▒
▒▒▒,k
R▒R&&NC▒Z▒O▒,[k▒
R▒▒*Ͳ▒▒▒▒▒▒▒▒Z!▒5R▒▒▒ѕ▒▒:▒▒▒ɥ▒▒▒չѕɁB▒Eu▒▒* R.V,WVHhWk▒S
W▒5▒k
...and from now on, it seems to work fine...
▒,PM▒▒00000: oscillator off
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 151 ha
U-Boot SPL 2022.01-rc3 (Aug 05 2022 - 11:10:07 +0200)
RAM: DDR3-DDR3L 32bits 533000kHz
stm32mp1_clk rcc@50000000: stm32mp1_clk_disable: id clock 228 has been disabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 220 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 222 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 226 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 229 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 224 has been enabled
id=15 clock = 1fc4ef40 : 533000 kHz
stm32mp1_clk rcc@50000000: computed rate for id clock 224 is 533000000 (parent
is PLL2_R)
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 228 has been enabled
get_ram_size(c0000000, 40000000)
info.size: 4
DDR invalid size : 0x4, expected 0x40000000
DRAM init failed: -22
### ERROR ### Please RESET the board ###
And it hangs here.
Looking with a oscilloscope, I can tell the STPMIC1 is not produce the
buck2 voltage for the DDR RAM (1.35V). It is 0V.
I suppose the SPL driver need to talk with i2c bus to it, and activate
the buck2 voltage as well as the other voltages.
All other voltages I can measure, they are fine, i.e. the VDD CORE is
between 1.2V or 1.35V, the VDD is 3.3V (buck3) and 3.3V in the buck4.
I don't know if the SPL code for power regulators is working fine, so
starting from device-tree point-of-view, it seems every pin involved
(pinmux), every device core involved (pinctrl_z, i2c4, pmic as node of
i2c4) has the correct tags to be built into the pre-relocation code:
u-boot,dm-pre-reloc;
status = "okay";
I would like to knwo how to increase or enable the serial debug output
for those drivers running in the SPL code. I have a batch of 10 boards,
and all are (non)working with the same error...
Thank you,
Gianluca
--
Eurek s.r.l. |
Electronic Engineering | http://www.eurek.it
via Celletta 8/B, 40026 Imola, Italy | Phone: +39-(0)542-609120
p.iva 00690621206 - c.f. 04020030377 | Fax: +39-(0)542-609212
