Thanks Stefan for your comments. Please see reply below.
>> + mtdcr(plb1_acr, plb1_acr_ppm_fair|
>> + plb1_acr_hbu_enabled |
>> + plb1_acr_rdp_4deep |
>> + plb1_acr_wrp_2deep);
>> +
>
>Is this PLB0_ACR tuning Canyonlands specif
On Thursday 07 August 2008, Prodyut Hazarika wrote:
> Set PL44 Arbiter Read pipeline depth to 4
> Optimize Memory Queue Configuration registers for PPC460EX/GT
>
> Signed-off-by: Prodyut Hazarika <[EMAIL PROTECTED]>
Thanks. Please find some comments below.
> ---
> board/amcc/canyonlands/canyonla
Set PL44 Arbiter Read pipeline depth to 4
Optimize Memory Queue Configuration registers for PPC460EX/GT
Signed-off-by: Prodyut Hazarika <[EMAIL PROTECTED]>
---
board/amcc/canyonlands/canyonlands.c |9 +++
cpu/ppc4xx/44x_spd_ddr2.c|4 +
include/ppc440.h |
