Dear Kumar Gala,
In message bcf2a946-e0cc-43f6-a875-a0e5a0de7...@kernel.crashing.org you wrote:
We don't use disable_law in the SPL code so only build it if
!CONFIG_NAND_SPL.
Does -ffunction-sections / --gc-sections not catch this automatically?
Doesn't appear to, but not sure if the
Hello Wolfgang,
Wolfgang Denk wrote:
In message 1299591018-8944-2-git-send-email...@denx.de you wrote:
- This patch reworks all headerfiles for keymile boards (coge, supx4,
eter1, suen3).
Furthermore, a refactoring on the whole environment variables has been
acomplished.
Two
Hello Wolfgang,
Wolfgang Denk wrote:
Dear Heiko Schocher,
In message 1299591018-8944-3-git-send-email...@denx.de you wrote:
- serial console on UART1
- Ethernet RMII over UCC4
- PHY SMSC LAN8700
- 64MB Flash
- 128 MB DDR2 RAM
- I2C
- bootcount
This board is similiar to the kmeter1
On 3/13/2011 12:41 PM, Harald Kipp wrote:
Add support for the Ethernut 5 open hardware design, based on Atmel's
AT91SAM9XE512 SoC.
NAK.
Too many trailing whitespaces and some more style issues. I haven't been
aware of the checkpatch script.
Regards,
Harald
PS: Seems to become a confirmed
Hi,
2011/3/13 Wolfgang Denk w...@denx.de:
Dear Nobuhiro Iwamatsu,
In message
1299484258-6042-1-git-send-email-nobuhiro.iwamatsu...@renesas.com you wrote:
Some board of SH does not have flash memoy.
This change initializes bi_flashstart, when CONFIG_SYS_FLASH_BASE was
defined,
Add i2c support to dkb board with pantheon soc.
Signed-off-by: Lei Wen lei...@marvell.com
---
arch/arm/cpu/arm926ejs/pantheon/cpu.c| 10 ++
arch/arm/include/asm/arch-pantheon/cpu.h |4 +++-
arch/arm/include/asm/arch-pantheon/mfp.h |2 ++
board/Marvell/dkb/dkb.c
Signed-off-by: Lei Wen lei...@marvell.com
---
arch/arm/cpu/pxa/cpu.c | 11 +++
arch/arm/include/asm/arch-pxa/pxa-regs.h | 56
board/innokom/innokom.c |9 +--
drivers/i2c/pxa_i2c.c| 139 +-
Signed-off-by: Lei Wen lei...@marvell.com
---
drivers/i2c/pxa_i2c.c | 38 --
include/configs/dkb.h |4 +++-
2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/pxa_i2c.c b/drivers/i2c/pxa_i2c.c
index 0e37417..17b83ab 100644
---
For better sharing with other platform other than pxa's,
it is more convenient to put the driver to the common place.
Signed-off-by: Lei Wen lei...@marvell.com
---
arch/arm/cpu/pxa/Makefile |1 -
arch/arm/cpu/pxa/i2c.c| 469 -
Signed-off-by: Lei Wen lei...@marvell.com
---
arch/arm/cpu/arm926ejs/armada100/cpu.c| 14 ++
arch/arm/include/asm/arch-armada100/mfp.h |4
board/Marvell/aspenite/aspenite.c |5 +
include/configs/aspenite.h| 12
4 files
Add support for the Ethernut 5 open hardware design, based
on Atmel's AT91SAM9XE512 SoC.
Signed-off-by: Harald Kipp harald.k...@egnite.de
---
V2:
- Fix several coding style issues.
- Remove Ethernet MAC address from default environment.
MAINTAINERS |3 +
On Mar 14, 2011, at 1:27 AM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message bcf2a946-e0cc-43f6-a875-a0e5a0de7...@kernel.crashing.org you
wrote:
We don't use disable_law in the SPL code so only build it if
!CONFIG_NAND_SPL.
Does -ffunction-sections / --gc-sections not catch this
On 03/12/2011 02:15 PM, Anatolij Gustschin wrote:
The reason for using wrsr register is that when reading this register,
we can also recognize the software reset cause (SWFT, bit 0 is set).
In our use case we have this requirement.
Ok, understood.
I do not think printing the reset cause
-Original Message-
From: Lei Wen [mailto:lei...@marvell.com]
Sent: Monday, March 14, 2011 3:46 PM
To: u-boot@lists.denx.de; Marek Vasut; Prafulla Wadaskar; Lei Wen
Subject: [PATCH 1/8] pxa: move i2c driver to the common place
For better sharing with other platform other than
Hello Wolfgang,
2011/3/13 Wolfgang Denk w...@denx.de:
Dear Daniel Schwierzeck,
In message 4d7c147a.5060...@gmail.com you wrote:
All current CPUs and SoCs are based on Mips32 arch. The complete
Is that true? What about purple SoC? IIUC It's based on MIPS 5Kc
and capable of 64-bit,
Dear Heiko,
In message 4d7dc1c1.4060...@denx.de you wrote:
+ im-sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE LAWBAR_BAR;
+ msize = fixed_sdram ();
Can we not use get_ram_size() ?
fixed_sdram calls this.
I see, thanks.
I see this:
[PATCH 01/20] keymile: rework headerfiles
Dear Daniel Schwierzeck,
In message aanlktinp-3rvxvkcxi8_xtra8mkobztv88vu2t1yk...@mail.gmail.com you
wrote:
OTOH, the purple board has not been actively maintained for several
years, and I'm not aware of anybody who still has access to the
hardware. =C2=A0If it should cause trouble, it
Hi List,
I tried crosscompiling fw_printenv lately (on 2011.03 RC1) but I kept
ending with a natively compiled version of fw_printenv. When looking at
the tools/env/Makefile I saw it was using $(HOSTCC) and friends, basicly
ever since:
Enable -march=armv7-a and Thumb build for OMAP4. This results in
Thumb2 code generated for OMAP4.
The newly added compiler switches are put under cc-option so
that it doesn't break old compilers.
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap4/config.mk | 25
Signed-off-by: Aneesh V ane...@ti.com
---
README |9 +
arch/arm/cpu/armv7/config.mk |5 +
2 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/README b/README
index f1547a4..ff3a345 100644
--- a/README
+++ b/README
@@ -370,6 +370,15 @@ The
On 03/14/2011 02:15 PM, Elie De Brauwer wrote:
Hi List,
I tried crosscompiling fw_printenv lately (on 2011.03 RC1) but I kept
ending with a natively compiled version of fw_printenv. When looking at
the tools/env/Makefile I saw it was using $(HOSTCC) and friends, basicly
ever since:
Dear Elie De Brauwer,
In message 4d7e14ed.1050...@gmail.com you wrote:
I tried crosscompiling fw_printenv lately (on 2011.03 RC1) but I kept
ending with a natively compiled version of fw_printenv. When looking at
the tools/env/Makefile I saw it was using $(HOSTCC) and friends, basicly
On 03/14/11 14:37, Stefano Babic wrote:
On 03/14/2011 02:15 PM, Elie De Brauwer wrote:
Hi List,
I tried crosscompiling fw_printenv lately (on 2011.03 RC1) but I kept
ending with a natively compiled version of fw_printenv. When looking at
the tools/env/Makefile I saw it was using $(HOSTCC)
Hi David,
It'd be good to include smdk2410 in this patch titles, eg smdk2410:
Various cleanups/code style fixes. or arm: smdk2410: Various...
Without the prefix, its unclear what code these patches affect, and
somewhat implies you are changing common code.
snip
-#define CONFIG_RTC_S3C24X0
Some ubi commands returned negative error codes, resulting in
the following error message on the prompt:
exit not allowed from main input shell.
Negative error codes are not allowed.
This patch now changes the UBI code to return positive error codes.
Additionally better error codes are used,
Hi Tom,
I'm not too familiar with the architecture, so many comments are
aesthetic. It would be a good idea to run the patch through
checkpatch.pl too.
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 684f2d2..50a1725 100644
--- a/arch/arm/cpu/armv7/start.S
+++
Albert,
On Sun, Mar 13, 2011 at 10:46 AM, Albert ARIBAUD albert.arib...@free.fr wrote:
Le 16/02/2011 21:26, Tom Warren a écrit :
Signed-off-by: Tom Warrentwar...@nvidia.com
---
arch/arm/cpu/armv7/start.S | 6 +
arch/arm/cpu/armv7/tegra2/Makefile | 2 +-
On Mon, Mar 14, 2011, Aneesh V wrote:
+- ARM Options:
+ CONFIG_SYS_THUMB_BUILD
+
+ Use this flag to build U-Boot using the Thumb instruction
+ set for ARM architectures. Thumb instruction set provides
+ better code density. For ARM
Hi!
On Mar 13, 2011, at 15:24, Wolfgang Denk wrote:
In message 1299519462-25320-2-git-send-email-kyle.d.moff...@boeing.com you
wrote:
In preparation for making system restart use a generic set of hooks for
boards and architectures, we define some wrappers and weak stubs.
The new wrapper
This is the latest respin of the eXMeritus HWW-1U-1A board support patches.
It's down to just a 3-patch series, with all of the other patches submitted
separately.
This series techncially depends on the reset rework, the reset command
will not work properly on the HWW-1U-1A hardware without those
To ease the implementation of other MPC85xx board ports, several common
GPIO helpers are added to asm/mpc85xx_gpio.h.
Since each of these compiles to no more than 4-5 instructions it would
be very inefficient to call them out of line, therefore we put them
entirely in the header file.
The
The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header. This dramatically improves the
readability of the switch statments.
In addition, a few of the longer lines were cleaned up, and the DDR2
type for an SO-RDIMM module was added to the DDR2
The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis
with 3 independent TEMPEST zones. Two independent P2020 computers may
be found inside each zone. Complete hardware support is included.
High-level hardware overview:
* DO-160 certified for passenger aircraft (noncritical)
*
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.
Since all of the inputs to this are 32-bit
On Thu, 2011-03-10 at 16:54 -0600, Peter Tyser wrote:
From: John Schmoller jschmol...@xes-inc.com
The JEDEC DDR3 specification states that the above parameters should
be set to a minimum of 4 clocks. The SPD defines the values in
nanoseconds, and depending on the clock frequency the value
On Sat, 12 Mar 2011 16:56:09 -0600
Kumar Gala ga...@kernel.crashing.org wrote:
On Mar 3, 2011, at 8:59 AM, Jimi Xenidis wrote:
I was surprised to find myself at the decrement interrupt when running my
new stuff.
That is against ePAPR, right?
Does u-boot at least make sure that the
On Mon, 2011-03-14 at 12:38 -0400, Kyle Moffett wrote:
The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header. This dramatically improves the
readability of the switch statments.
In addition, a few of the longer lines were cleaned up,
On Mon, 2011-03-14 at 12:38 -0400, Kyle Moffett wrote:
The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header. This dramatically improves the
readability of the switch statments.
In addition, a few of the longer lines were cleaned up,
Dear Moffett, Kyle D,
In message a60aea13-1206-4699-9302-0df9c0f9d...@boeing.com you wrote:
The new wrapper functions are:
system_restart() - Normal system reboot (IE: user request)
emergency_restart() - Critical error response (IE: panic(), etc)
What is the difference
Dear Kumar Gala,
In message alpine.lfd.2.00.1103140036490.3...@right.am.freescale.net you
wrote:
A few fixes for v2011.03 release.
The following changes since commit c7977858dcf1f656cbe91ea0dc3cb9139c6a8cc8:
ARM: Update mach-types (2011-02-21 08:30:55 +0100)
are available in the git
On Mar 14, 2011, at 1:09 PM, Scott Wood wrote:
On Sat, 12 Mar 2011 16:56:09 -0600
Kumar Gala ga...@kernel.crashing.org wrote:
On Mar 3, 2011, at 8:59 AM, Jimi Xenidis wrote:
I was surprised to find myself at the decrement interrupt when running my
new stuff.
That is against ePAPR,
On Mar 14, 2011, at 14:59, Wolfgang Denk wrote:
In message a60aea13-1206-4699-9302-0df9c0f9d...@boeing.com you wrote:
My own board needs both processor modules to synchronize resets to allow
them to come back up at all, which means that a reset may block for an
arbitrary amount of time waiting
Kyle,
On Mon, 2011-03-14 at 14:04 -0500, Moffett, Kyle D wrote:
On 64-bit this change is basically a no-op, because do_div() is implemented
as a literal 64-bit divide operation and the instruction scheduling works out
almost the same.
On 32-bit PowerPC a fully accurate 64/64 divide
On Mar 14, 2011, at 15:41, York Sun wrote:
Kyle,
On Mon, 2011-03-14 at 14:04 -0500, Moffett, Kyle D wrote:
On 64-bit this change is basically a no-op, because do_div() is implemented
as a literal 64-bit divide operation and the instruction scheduling works
out almost the same.
On
On Mar 14, 2011, at 14:19, York Sun wrote:
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
+ * Now divide by 5^12 and track the 32-bit remainder, then divide
+ * by 2*(2^12) using shifts (and updating the remainder).
+ */
+ clks_rem = do_div(clks, UL_5pow12);
+ clks_rem = 13;
Shouldn't this be clks_rem =
Update the monitor environment variable (for Freescale chips that have a
DIU display controller) to designate the full video configuration, instead
of just the output monitor.
The old definition of the monitor environment variable only determines
which video port to use for output. This variable
Dear Moffett, Kyle D,
In message 613c8f89-3ce5-4c28-a48e-d5c3e8143...@boeing.com you wrote:
On our boards, when the reset button is pressed in hardware, both
processor modules on the board and all the attached hardware reset at
the same time.
OK. So a sane design would provide a way for
The bus that the i2c api can access before relocating from flash
is defined via CONFIG_SYS_SPD_BUS_NUM, however we want to use
the i2c bus before relocating from flash for non-SPD related
reasons. Therefore, we rename this define to something more
appropriate
---
We are trying to access the I2C
All current Mips CPUs and SoCs except Purple are based on Mips32 arch.
The complete code resides in the global arch/mips/cpu directory.
All SoC specific code resides in this directory too. This is not suitable
if other Mips architectures like Mips64 or Octeon or new SoCs should be
supported in the
The Purple SoC and eval board are not actively maintained since years.
This patch removes the support completely as aggreed with Wolfgang Denk.
Signed-off-by: Daniel Schwierzeck daniel.schwierz...@googlemail.com
Cc: Shinya Kuribayashi skuri...@pobox.com
Cc: Wolfgang Denk w...@denx.de
---
All current CPUs and SoCs are based on Mips32 arch. The complete
code resides in the global arch/mips/cpu directory. This is not
suitable if other Mips architectures like Mips64 or Octeon should
be supported in the future.
To achieve this the current CPU code is moved to its own mips32
Au1x00 is a SoC and its specific code should reside in an own
SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.
Signed-off-by: Daniel Schwierzeck daniel.schwierz...@googlemail.com
Cc: Shinya Kuribayashi skuri...@pobox.com
Cc: Thomas Lange tho...@corelatus.se
---
The current Mips CPU config.mk code always expects a Mips 4kc
core and toolchain. This is not appropiate for other toolchains
and CPUs/SoCs.
Replace the current MIPSFLAGS code by cc-option macro and use
-march=mips32r2 as default optimization level for all Mips32 CPUs.
Replace the endianess
Peter,
On Mon, Mar 14, 2011 at 8:33 AM, Peter Tyser pty...@xes-inc.com wrote:
Hi Tom,
I'm not too familiar with the architecture, so many comments are
aesthetic. It would be a good idea to run the patch through
checkpatch.pl too.
I run checkpatch on every submission. Only 1 warning was
On Mar 14, 2011, at 16:38, Wolfgang Denk wrote:
In message 613c8f89-3ce5-4c28-a48e-d5c3e8143...@boeing.com you wrote:
If just *one* of the 2 CPUs triggers the reset then only *some* of
the attached hardware will be properly reset due to a hardware
errata, and as a result the board will
IncaIP is a SoC and its specific code should reside in an own
SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.
Signed-off-by: Daniel Schwierzeck daniel.schwierz...@googlemail.com
Cc: Shinya Kuribayashi skuri...@pobox.com
Cc: Wolfgang Denk w...@denx.de
---
On Mar 14, 2011, at 1:09 PM, Scott Wood wrote:
On Sat, 12 Mar 2011 16:56:09 -0600
Kumar Gala ga...@kernel.crashing.org wrote:
On Mar 3, 2011, at 8:59 AM, Jimi Xenidis wrote:
I was surprised to find myself at the decrement interrupt when running my
new stuff.
That is against ePAPR,
On Mar 14, 2011, at 16:22, York Sun wrote:
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
+ * Now divide by 5^12 and track the 32-bit remainder, then divide
+ * by 2*(2^12) using shifts (and updating the remainder).
+ */
+clks_rem = do_div(clks, UL_5pow12);
+
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.
Since all of the inputs to this are 32-bit
On Mon, 14 Mar 2011 16:25:54 -0500
Kumar Gala ga...@kernel.crashing.org wrote:
On Mar 14, 2011, at 1:09 PM, Scott Wood wrote:
On Sat, 12 Mar 2011 16:56:09 -0600
Kumar Gala ga...@kernel.crashing.org wrote:
On Mar 3, 2011, at 8:59 AM, Jimi Xenidis wrote:
I was surprised to
Dear Moffett, Kyle D,
In message 44a75130-ed4f-46d6-b0e4-12433cc15...@boeing.com you wrote:
Oh, absolutely. I do think there still needs to be a separation
between a normal user-initiated restart and an panic-time
emergency restart though, see further on in this email.
These terms refer to
Hi Tom,
snip
+static void init_pll_x(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE;
+ u32 reg;
The spaces in front of reg can be removed. Ditto for all
functions/variables.
Not sure what you mean, here, Peter. There are no
Peter,
On Mon, Mar 14, 2011 at 3:20 PM, Peter Tyser pty...@xes-inc.com wrote:
Hi Tom,
snip
+static void init_pll_x(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST
_BASE;
+ u32 reg;
The spaces in front of reg can be removed. Ditto for
Dear Matthew McClintock,
In message 1300135645-21544-1-git-send-email-...@freescale.com you wrote:
The bus that the i2c api can access before relocating from flash
is defined via CONFIG_SYS_SPD_BUS_NUM, however we want to use
the i2c bus before relocating from flash for non-SPD related
Dear Timur Tabi,
In message 1300133949-1115-1-git-send-email-ti...@freescale.com you wrote:
Update the monitor environment variable (for Freescale chips that have a
DIU display controller) to designate the full video configuration, instead
of just the output monitor.
The old definition of
Wolfgang Denk wrote:
Looks as if this was a Freescale specific implementation?
Yes.
Can this not be turned into generic code, usable for other boards /
systems as well?
Possibly, but I would like to fix one bug at a time.
Please see the discussion we had about video modes for the i.MX
On Mon, Mar 14, 2011 at 6:28 PM, Wolfgang Denk w...@denx.de wrote:
We are trying to access the I2C bus before relocation from flash to read
switch settings. Using the current CONFIG_SYS_SPD_BUS_NUM define to do this
is fine for our needs however I would like to ask if we wanted to change
this
On 3/15/11 6:14 AM, daniel.schwierz...@googlemail.com wrote:
Replace the current MIPSFLAGS code by cc-option macro and use
-march=mips32r2 as default optimization level for all Mips32 CPUs.
Replace the endianess determination code from toolchain prefix by
a more generic one inspired by the
Seperating the SOCs solves most of my problems with the exception of board.c,
but then again, we're rather a special case there due to some of the stuff we
do.
Not counting our SDK we have around 27Kloc for our platform, a large chunk of
that being DDR2/3 memory initialization code. Our SDK
Hi Prafulla,
On Mon, Mar 14, 2011 at 8:03 PM, Prafulla Wadaskar prafu...@marvell.com wrote:
-Original Message-
From: Lei Wen [mailto:lei...@marvell.com]
Sent: Monday, March 14, 2011 3:46 PM
To: u-boot@lists.denx.de; Marek Vasut; Prafulla Wadaskar; Lei Wen
Subject: [PATCH 1/8] pxa:
Dear Wolfgang,
On 14 March 2011 04:50, Wolfgang Denk w...@denx.de wrote:
Dear Minkyu Kang,
In message 4d75b591.3040...@samsung.com you wrote:
If FB address is defined specific address then don't grab memory for LCD
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
Cc: Albert Aribaud
On 02/28/2011 03:57 PM, Xiangfu Liu wrote:
diff --git a/arch/mips/cpu/xburst/jz_serial.c
b/arch/mips/cpu/xburst/jz_serial.c
new file mode 100644
index 000..65ce993
--- /dev/null
+++ b/arch/mips/cpu/xburst/jz_serial.c
[...]
+/*
+ * serial_init - initialize a channel
+ *
+ * This
On 02/28/2011 03:57 PM, Xiangfu Liu wrote:
this is jz4740 base head file
Signed-off-by: Xiangfu Liu xian...@openmobilefree.net
Acked-by: Daniel z...@ingenic.cn
---
Changes for v2:
- remove useless code, prepare for using io.h
- delete all base + offset. using C struct
On 02/28/2011 03:57 PM, Xiangfu Liu wrote:
arch/mips/cpu/xburst/Makefile| 50 +++
arch/mips/cpu/xburst/config.mk | 33 ++
arch/mips/cpu/xburst/cpu.c | 160
arch/mips/cpu/xburst/jz4740.c| 264
arch/mips/cpu/xburst/jz_serial.c | 114 +
On 02/28/2011 03:57 PM, Xiangfu Liu wrote:
diff --git a/Makefile b/Makefile
index dc2e3d8..758daf2 100644
--- a/Makefile
+++ b/Makefile
@@ -1093,6 +1093,19 @@ smdk6400_config: unconfig
@echo CONFIG_NAND_U_BOOT = y $(obj)include/config.mk
V2:
rename the previous pxa_i2c to mvi2c, since this driver would be shared
by many other Marvell platforms.
Lei Wen (5):
pxa: move i2c driver to the common place
mvi2c: use structure to replace the direclty define
I2C: add i2c support for Pantheon platform
I2C: mvi2c: add multi bus
Signed-off-by: Lei Wen lei...@marvell.com
---
arch/arm/cpu/pxa/cpu.c | 11 +++
arch/arm/include/asm/arch-pxa/pxa-regs.h | 56
board/innokom/innokom.c |9 +--
drivers/i2c/mvi2c.c | 139 +-
Add i2c support to dkb board with pantheon soc.
Signed-off-by: Lei Wen lei...@marvell.com
---
arch/arm/cpu/arm926ejs/pantheon/cpu.c| 10 ++
arch/arm/include/asm/arch-pantheon/cpu.h |4 +++-
arch/arm/include/asm/arch-pantheon/mfp.h |2 ++
board/Marvell/dkb/dkb.c
Signed-off-by: Lei Wen lei...@marvell.com
---
drivers/i2c/mvi2c.c | 37 -
1 files changed, 36 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/mvi2c.c b/drivers/i2c/mvi2c.c
index 0e37417..ca1add8 100644
--- a/drivers/i2c/mvi2c.c
+++
Signed-off-by: Lei Wen lei...@marvell.com
---
arch/arm/cpu/arm926ejs/armada100/cpu.c| 14 ++
arch/arm/include/asm/arch-armada100/mfp.h |4
board/Marvell/aspenite/aspenite.c |5 +
include/configs/aspenite.h| 12
4 files
For better sharing with other platform other than pxa's,
it is more convenient to put the driver to the common place.
Signed-off-by: Lei Wen lei...@marvell.com
---
Changelog:
v2: rename previous pxa_i2c to mvi2c.
arch/arm/cpu/pxa/Makefile |1 -
arch/arm/cpu/pxa/i2c.c| 469
Loic,
On Monday 14 March 2011 09:41 PM, Loïc Minier wrote:
On Mon, Mar 14, 2011, Aneesh V wrote:
+- ARM Options:
+CONFIG_SYS_THUMB_BUILD
+
+Use this flag to build U-Boot using the Thumb instruction
+set for ARM architectures. Thumb instruction set
This patch enables compiler debug option for powerpc platforms
by default. Patch is tested on 85xx/QorIQ platforms in u-boot
with CodeWarrior.
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Cc: Wood Scott-B07421 b07...@freescale.com
Cc: Kumar Gala ga...@kernel.crashing.org
---
Consider the
On Mar 14, 2011, at 2:39 PM, Jimi Xenidis wrote:
On Mar 14, 2011, at 1:09 PM, Scott Wood wrote:
On Sat, 12 Mar 2011 16:56:09 -0600
Kumar Gala ga...@kernel.crashing.org wrote:
On Mar 3, 2011, at 8:59 AM, Jimi Xenidis wrote:
I was surprised to find myself at the decrement interrupt
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