Acked-by: Sonic Zhang sonic.zh...@analog.com
Thanks,
Sonic
-Original Message-
From: Masahiro Yamada [mailto:yamad...@jp.panasonic.com]
Sent: Thursday, July 03, 2014 12:56 PM
To: u-boot@lists.denx.de
Cc: Masahiro Yamada; Stefan Roese; Zhang, Sonic
Subject: [PATCH] blackfin,powerpc:
Hi U-boot team,
I am looking for u-boot command which can give me flash device specific
properties. For example, there should be dedicated commands to get the
flash memory size, sector size, page size etc.
Currently I found there is command sf probe for spi flash device which is
returning device
From: Dirk Eibach dirk.eib...@gdsys.cc
Changes in v3:
- describe ihs_i2c in README
Changes in v2:
- make sha256 support optional
- move ihs_i2c to drivers/i2c
- split unrelated changes
- use defines for I2C bus numbers
Dirk Eibach (13):
board: controlcenterd: Fix pci access
board: gdsys:
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/p1022/sdhc_boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2:
- use defines for I2C bus numbers
board/gdsys/p1022/controlcenterd-id.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git
From: Dirk Eibach dirk.eib...@gdsys.cc
Commit 2842c1c fit: add sha256 support badly increased
memory footprint, so some of our boards did not build anymore.
Since monitor base must not be changed I removed some commands
to save memory.
Maybe making sha256 optional for fit would be an option for
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
include/configs/dlvision-10g.h | 2 +-
include/configs/iocon.h| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Dirk Eibach dirk.eib...@gdsys.cc
The I2C bridge on DP501 supports EDID, MCCS and HDCP by default.
Allow EDID only to avoid I2C address conflicts.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/common/dp501.c | 1 +
From: Dirk Eibach dirk.eib...@gdsys.cc
There is a new iocon hardware flavor, supporting DisplayPort finally.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 12 +
board/gdsys/common/Makefile | 2 +-
From: Dirk Eibach dirk.eib...@gdsys.cc
To avoid peer ChReceivePathStatus-messages on iocon startup, initialize
PHYs as soon as possible.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 9 -
1 file changed, 4
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 17 ++-
board/gdsys/common/osd.c | 113 +++--
drivers/i2c/ihs_i2c.c | 1
From: Dirk Eibach dirk.eib...@gdsys.cc
readl was called with values instead of pointers to these values.
Why this ever did work is a mystery...
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/p1022/controlcenterd.c | 6 +++---
1 file
From: Dirk Eibach dirk.eib...@gdsys.cc
For proper displayport performance, scrambling has to be enabled, but
is turned off on DP501 by default.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/common/dp501.c | 1 +
1 file changed, 1
From: Dirk Eibach dirk.eib...@gdsys.cc
sha256 has some beefy memory footprint.
Make it optional for constrained systems.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2:
- make sha256 support optional
include/configs/dlvision-10g.h | 1 +
From: Dirk Eibach dirk.eib...@gdsys.cc
IHS I2C master support was merely a hack in the osd driver.
Now it is a proper u-boot I2C framework driver, supporting the
v2.00 master features.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3:
- describe ihs_i2c in README
Changes in
From: Dirk Eibach dirk.eib...@gdsys.cc
PPC4xx config options were not complete.
ICS8N3QV01 and SIL1178 needed some more configuration.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
include/configs/dlvision-10g.h | 10 --
1 file changed, 8
Hi Darwin,
On Mon, 9 Jun 2014 11:12:59 -0700, Darwin Rambo dra...@broadcom.com
wrote:
The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF
images and u-boot, and does this for virtual platforms by using
semihosting. This commit extends this idea by allowing u-boot to also
use
On 03.07.2014 08:27, dirk.eib...@gdsys.cc wrote:
From: Dirk Eibach dirk.eib...@gdsys.cc
Looks good for the ppc4xx parts, so:
Acked-by: Stefan Roese s...@denx.de
Thanks,
Stefan
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Hello Dirk,
Am 03.07.2014 08:27, schrieb dirk.eib...@gdsys.cc:
From: Dirk Eibachdirk.eib...@gdsys.cc
IHS I2C master support was merely a hack in the osd driver.
Now it is a proper u-boot I2C framework driver, supporting the
v2.00 master features.
Signed-off-by: Dirk Eibachdirk.eib...@gdsys.cc
Hello Dirk,
Am 03.07.2014 08:27, schrieb dirk.eib...@gdsys.cc:
From: Dirk Eibachdirk.eib...@gdsys.cc
sha256 has some beefy memory footprint.
Make it optional for constrained systems.
Signed-off-by: Dirk Eibachdirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2:
- make sha256 support
Hi Fabio,
On 02/07/2014 20:54, Fabio Estevam wrote:
Hi Stefano,
On Tue, Jun 24, 2014 at 5:40 PM, Fabio Estevam feste...@gmail.com wrote:
From: Fabio Estevam fabio.este...@freescale.com
mx6solox is the newest member of the mx6 family.
Some of the new features on this variants are:
-
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/p1022/sdhc_boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/gdsys/p1022/sdhc_boot.c
From: Dirk Eibach dirk.eib...@gdsys.cc
IHS I2C master support was merely a hack in the osd driver.
Now it is a proper u-boot I2C framework driver, supporting the
v2.00 master features.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3:
- describe ihs_i2c in
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- use defines for I2C bus numbers
board/gdsys/p1022/controlcenterd-id.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/configs/dlvision-10g.h | 2 +-
include/configs/iocon.h| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Dirk Eibach dirk.eib...@gdsys.cc
readl was called with values instead of pointers to these values.
Why this ever did work is a mystery...
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/p1022/controlcenterd.c |
From: Dirk Eibach dirk.eib...@gdsys.cc
sha256 has some beefy memory footprint.
Make it optional for constrained systems.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4:
- describe CONFIG_FIT_DISABLE_SHA256 in README
Changes in v3: None
Changes in v2:
- make sha256 support
From: Dirk Eibach dirk.eib...@gdsys.cc
The I2C bridge on DP501 supports EDID, MCCS and HDCP by default.
Allow EDID only to avoid I2C address conflicts.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/common/dp501.c
From: Dirk Eibach dirk.eib...@gdsys.cc
PPC4xx config options were not complete.
ICS8N3QV01 and SIL1178 needed some more configuration.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/configs/dlvision-10g.h | 10 --
From: Dirk Eibach dirk.eib...@gdsys.cc
There is a new iocon hardware flavor, supporting DisplayPort finally.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 12 +
board/gdsys/common/Makefile |
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 17 ++-
board/gdsys/common/osd.c | 113 +++--
From: Dirk Eibach dirk.eib...@gdsys.cc
For proper displayport performance, scrambling has to be enabled, but
is turned off on DP501 by default.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/common/dp501.c | 1 +
1
From: Dirk Eibach dirk.eib...@gdsys.cc
To avoid peer ChReceivePathStatus-messages on iocon startup, initialize
PHYs as soon as possible.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 9 -
1
From: Dirk Eibach dirk.eib...@gdsys.cc
Changes in v4:
- describe CONFIG_FIT_DISABLE_SHA256 in README
Changes in v3:
- describe ihs_i2c in README
Changes in v2:
- make sha256 support optional
- move ihs_i2c to drivers/i2c
- split unrelated changes
- use defines for I2C bus numbers
Dirk Eibach
From: Dirk Eibach dirk.eib...@gdsys.cc
Commit 2842c1c fit: add sha256 support badly increased
memory footprint, so some of our boards did not build anymore.
Since monitor base must not be changed I removed some commands
to save memory.
Maybe making sha256 optional for fit would be an option for
Dear Stephen,
In message 53b47f6f.1090...@wwwdotorg.org you wrote:
Is there a specific reason for not using get_ram_size()?
Since we know the exact RAM size, we may as well simply use it directly
rather than probing for it.
You _think_ you know the size, but you can never be sure that all
patman has decided to send some patches of the v4 series with a v3 label.
I am not sure what to do about this. Ideas anybody?
Cheers
Dirk
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Hi U-boot team,
I am looking for u-boot command which can give me flash device specific
properties. For example, there should be dedicated commands to get the
flash memory size, sector size, page size etc.
Currently I found there is command sf probe for spi flash device which
is returning
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Add private mdio read and write support.
drivers/net/fsl_mdio.c | 24 +++-
drivers/net/tsec.c | 7 +++
include/fsl_mdio.h | 3 +++
include/tsec.h | 7 ++-
4 files changed, 35
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: no change.
drivers/mmc/fsl_esdhc.c | 4 ++--
include/fsl_esdhc.h | 14 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index
From: Claudiu Manoil claudiu.man...@freescale.com
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR
board.
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From: York Sun york...@freescale.com
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: New file.
board/freescale/ls1021atwr/Makefile | 7 +
board/freescale/ls1021atwr/README | 109 +++
board/freescale/ls1021atwr/ls1021atwr.c | 499
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank.
From: York Sun york...@freescale.com
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun york...@freescale.com
---
Change log:
v2: no change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
1 file changed,
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: no change.
drivers/i2c/mxc_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 48468d7..792fc40 100644
--- a/drivers/i2c/mxc_i2c.c
+++
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Change log:
v2: Remove ethaddr/ipaddr
patman has decided to send some patches of the v4 series with a v3 label.
I am not sure what to do about this. Ideas anybody?
Ooops, sorry for the noise.
patman did it right and sent v4 labels.
It was just Gmail being extrasmart and grouping them in a thread. So
only the first subject is shown.
Hi,
On 07/03/2014 01:20 AM, Benoît Thébaudeau wrote:
)Dear Helmut Raiger,
On Wed, Jul 2, 2014 at 9:04 AM, Helmut Raiger helmut.rai...@hale.at wrote:
the commit 41623c91 breaks the SPL on i.mx31 platforms.
Here, you are talking about mx31pdk, right?
Actually im talking TT-01, but it
Hi Pantelis, Tom,
Apparently, Dmitry has sent the message in html format...
Resending now...
Sorry for that...
Original Message
Subject:Re: [U-Boot] [PATCH 2/3] env_mmc: support env partition setup
in runtime
Date: Wed, 25 Jun 2014 10:42:11 +0300
From: Dmitry
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's
frequency need to config here.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 4 ++--
1 file changed, 2
For some SoCs, the pen address may has different endianness with
the CPUs, so this need the byte revertion for it,
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S
To enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the LS1021A
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +--
board/freescale/ls1021aqds/ls1021aqds.c | 110 +++--
board/freescale/ls1021atwr/ls1021atwr.c | 111 --
3 files
On Thu, Jul 03, 2014 at 09:45:52AM +0200, Wolfgang Denk wrote:
Dear Stephen,
In message 53b47f6f.1090...@wwwdotorg.org you wrote:
Is there a specific reason for not using get_ram_size()?
Since we know the exact RAM size, we may as well simply use it directly
rather than probing for
On 07/03/2014 12:51 PM, Xiubo Li wrote:
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence
On 07/03/2014 12:51 PM, Xiubo Li wrote:
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.
Can you give an example?
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's
frequency need to config here.
Signed-off-by: Xiubo Li
On 07/03/2014 12:51 PM, Xiubo Li wrote:
To enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address
On 07/03/2014 12:51 PM, Xiubo Li wrote:
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +--
board/freescale/ls1021aqds/ls1021aqds.c | 110 +++--
board/freescale/ls1021atwr/ls1021atwr.c
Hi Alison,
On Thu, 3 Jul 2014 15:24:14 +0800, Alison Wang b18...@freescale.com
wrote:
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR
board.
The numbering in the cover letter (0/9) does not match that in the
individual patches (n/10). Is this normal?
Hi Helmut,
On Thu, 03 Jul 2014 10:19:39 +0200, Helmut Raiger
helmut.rai...@hale.at wrote:
Hi,
On 07/03/2014 01:20 AM, Benoît Thébaudeau wrote:
)Dear Helmut Raiger,
On Wed, Jul 2, 2014 at 9:04 AM, Helmut Raiger helmut.rai...@hale.at wrote:
the commit 41623c91 breaks the SPL on
Hi, Albert,
On Thu, 3 Jul 2014 15:24:14 +0800, Alison Wang
wrote:
This series contain the support for Freescale LS102xA SoC and
LS1021AQDS/TWR board.
The numbering in the cover letter (0/9) does not match that in the
individual patches (n/10). Is this normal?
Sorry, it's my mistake. It
Hi Ian,
Hans and I would like to propose the creation of a uboot-sunxi.git
custodian tree for things relating to the Allwinner platforms. It would
be a downstream of uboot-arm.git tree with responsibility for it shared
between us. This was previously mentioned on list[0] but we figured it
On 07/02/2014 04:36 PM, Ivan Khoronzhuk wrote:
Add script to automate NAND flash process. As for now the board has
two burn scripts - burn to boot from SPI NOR flash and burn to boot
from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi.
Also update README to contain NAND burn U-boot
On 07/03/2014 06:11 PM, Murali Karicheri wrote:
On 07/02/2014 04:36 PM, Ivan Khoronzhuk wrote:
Add script to automate NAND flash process. As for now the board has
two burn scripts - burn to boot from SPI NOR flash and burn to boot
from AEMIF NAND flash, rename burn_uboot script to
Hi,
On 3 July 2014 00:03, Heiko Schocher h...@denx.de wrote:
Hello Dirk,
Am 03.07.2014 08:27, schrieb dirk.eib...@gdsys.cc:
From: Dirk Eibachdirk.eib...@gdsys.cc
sha256 has some beefy memory footprint.
Make it optional for constrained systems.
Signed-off-by: Dirk
Hi,
On 22 June 2014 20:31, tiger...@via-alliance.com wrote:
Hi, experts:
I am studying u-boo.bin format(which is got from u-boot, an ELF format
bin).
I run the below command:
Objdump -h -b binary -m arm u-boot.bin
Found only a .data section was displayed.
So , does u-boot.bin
Hi,
On 2 July 2014 10:05, HEERA NAND BHAGTANI diamond@gmail.com wrote:
Hi U-boot team,
I am looking for u-boot command which can give me flash device specific
properties. For example, there should be dedicated commands to get the
flash memory size, sector size, page size etc.
Currently
Hi Stefano,
On Thu, Jul 3, 2014 at 4:15 AM, Stefano Babic sba...@denx.de wrote:
I have only taken a short look because the series should flow after
2014.07. Anyway, I could push them into -next.
Pushing them into -next would be very helpful, so that we can continue
on adding new support for
On Thu, Jul 03, 2014 at 09:14:01AM -0700, Simon Glass wrote:
Hi,
On 3 July 2014 00:03, Heiko Schocher h...@denx.de wrote:
Hello Dirk,
Am 03.07.2014 08:27, schrieb dirk.eib...@gdsys.cc:
From: Dirk Eibachdirk.eib...@gdsys.cc
sha256 has some beefy memory footprint.
Make it
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Fri, Jun 27, 2014 at 3:24 PM, Stefan Roese s...@denx.de wrote:
Add ID for this Numonix / STMicro chip.
Tested on Marvell DB-78460-BP board.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Jagannadha Sutradharudu Teki
May possible to include in different patch.
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Fri, Jun 27, 2014 at 3:24 PM, Stefan Roese s...@denx.de wrote:
Signed-off-by: Stefan Roese s...@denx.de
Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Fri, Jun 27, 2014 at 3:24 PM, Stefan Roese s...@denx.de wrote:
This patch introduces the clrsetbits_le32() accessor functions in the
kirkwood SPI driver. Note that it also includes a fix:
-writel(~KWSPI_CSN_ACT |
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Fri, Jun 27, 2014 at 3:24 PM, Stefan Roese s...@denx.de wrote:
Signed-off-by: Stefan Roese s...@denx.de
Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
arch/arm/include/asm/arch-kirkwood/spi.h | 8
1 file
On Fri, Jun 13, 2014 at 2:23 AM, Marek Vasut ma...@denx.de wrote:
It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory. Also, add a debug output
when BAR configuration fails to follow suit.
Signed-off-by: Marek Vasut ma...@denx.de
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Fri, Jun 27, 2014 at 3:24 PM, Stefan Roese s...@denx.de wrote:
Signed-off-by: Stefan Roese s...@denx.de
Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/spi/kirkwood_spi.c | 14 ++
1 file changed, 6
Signed-off-by: Ian Campbell i...@hellion.org.uk
Cc: Hans de Goede hdego...@redhat.com
---
doc/git-mailrc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 251586e..d924b26 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -17,10 +17,12 @@ alias ag
Thanks! for the document.
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Tue, Jul 1, 2014 at 5:00 PM, Josh Wu josh...@atmel.com wrote:
The option can be used to save the environment in spi flash.
Implementation code is already exist in command/env_sf.c. But
the documentation
Hi,
On 07/03/2014 10:25 PM, Ian Campbell wrote:
Signed-off-by: Ian Campbell i...@hellion.org.uk
Cc: Hans de Goede hdego...@redhat.com
ACK.
Acked-by: Hans de Goede hdego...@redhat.com
Regards,
Hans
---
doc/git-mailrc | 3 +++
1 file changed, 3 insertions(+)
diff --git
Hi,
On Thu, Jul 3, 2014 at 10:19 AM, Helmut Raiger helmut.rai...@hale.at wrote:
On 07/03/2014 01:20 AM, Benoît Thébaudeau wrote:
)Dear Helmut Raiger,
On Wed, Jul 2, 2014 at 9:04 AM, Helmut Raiger helmut.rai...@hale.at
wrote:
the commit 41623c91 breaks the SPL on i.mx31 platforms.
Hi Albert,
On Thu, Jul 3, 2014 at 3:35 PM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Helmut,
On Thu, 03 Jul 2014 10:19:39 +0200, Helmut Raiger
helmut.rai...@hale.at wrote:
Hi,
On 07/03/2014 01:20 AM, Benoît Thébaudeau wrote:
)Dear Helmut Raiger,
On Wed, Jul 2, 2014 at 9:04
On Thursday, July 03, 2014 at 10:24:44 PM, Jagan Teki wrote:
On Fri, Jun 13, 2014 at 2:23 AM, Marek Vasut ma...@denx.de wrote:
It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory. Also, add a debug output
when BAR configuration
On Fri, Jun 27, 2014 at 11:55:09AM +0200, Stefan Roese wrote:
Signed-off-by: Stefan Roese s...@denx.de
---
tools/Makefile | 1 +
1 file changed, 1 insertion(+)
Tested-by: Luka Perkov l...@openwrt.org
Luka
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Hi Stefan,
On Fri, Jun 27, 2014 at 11:55:08AM +0200, Stefan Roese wrote:
The barebox version of the kwboot tool has evolved a bit. To support
Armada XP and Dove. Additionally a few minor fixes have been applied.
So lets sync with the latest barebox version.
Please note that the main
On Fri, Jun 27, 2014 at 11:55:10AM +0200, Stefan Roese wrote:
This patch integrates the Barebox version of this kwbimage.c file into
U-Boot. As this version supports the image version 1 type for the
Armada XP / 370 SoCs.
It was easier to integrate the existing and known to be working Barebox
Hello Dirk, Tom, Simon,
Am 03.07.2014 21:17, schrieb Tom Rini:
On Thu, Jul 03, 2014 at 09:14:01AM -0700, Simon Glass wrote:
Hi,
On 3 July 2014 00:03, Heiko Schocherh...@denx.de wrote:
Hello Dirk,
Am 03.07.2014 08:27, schrieb dirk.eib...@gdsys.cc:
From: Dirk Eibachdirk.eib...@gdsys.cc
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d639a6f..f090971 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -18,6 +18,15 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_EARLY_INIT_R
+#define
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may
Subject: Re: [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.
On 07/03/2014 12:51 PM, Xiubo Li wrote:
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.
Can you give an example?
In LS1021A-QDS/TWR, the CONFIG_SYS_CLK_FREQ is 100Mhz and the ARCH
- reg = in_be32(csu_csl2);
- out_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS |
- CSU_CSL2x_NS_USER_READ_ACCESS);
+void enable_devices_ns_access(void)
This function is identical for twr and qds? Can't be just one in a
common file?
Sure, I will follow your
Whatever we do: we have some broken boards, so please let us fix it before
next release.
I am off on vacation now. If necessary simply drop this patch from the
series.
Cheers
Dirk
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U-Boot@lists.denx.de
It's reasonable, looks good to me.
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
This change fixes the bad gpio configuration for the exynos dwmmc.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Beomho Seo
Hi, Przemyslaw.
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
It is possible to boot device using a micro SD or eMMC slots.
In this situation, boot device should be registered as a block
device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV
is usually set to 0 in the most config
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
This change adds declaration of functions:
- set_board_type() - called at checkboard()
- get_board_type() - called at checkboard()
- get_board_name()
For supporting multiple board types in a one config - it is welcome
to display the current
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