Hello Albert,
On Sat, 8 Nov 2014 08:43:16 +0100, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hello Arnab,
On Thu, 28 Aug 2014 01:59:54 +0530, Arnab Basu
arnab.b...@freescale.com wrote:
Signed-off-by: Arnab Basu arnab.b...@freescale.com
Reviewed-by: Bhupesh Sharma
Hello Steve,
On Fri, 7 Nov 2014 18:13:18 -0800, Steve Rae s...@broadcom.com wrote:
- 5 based on cygnus, 2 based on 28155
- updates to support board families better
- add functions so CONFIG_ARMV7_NONSEC can be enabled on Cygnus boards
Signed-off-by: Steve Rae s...@broadcom.com
---
Could
Hello Thierry,
On Tue, 26 Aug 2014 17:34:20 +0200, Thierry Reding thierry.red...@gmail.com
wrote:
From: Thierry Reding tred...@nvidia.com
Remove two gratuituous blank lines, uses u32 (instead of int) as the
type for values that will be written to a register, moves the beginning
of the
Hello Thierry,
On Tue, 26 Aug 2014 17:34:21 +0200, Thierry Reding thierry.red...@gmail.com
wrote:
From: Thierry Reding tred...@nvidia.com
size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit,
Hello Thierry,
On Tue, 26 Aug 2014 17:34:22 +0200, Thierry Reding thierry.red...@gmail.com
wrote:
From: Thierry Reding tred...@nvidia.com
When DEBUG is set, output memory region used for malloc().
Signed-off-by: Thierry Reding tred...@nvidia.com
---
common/dlmalloc.c | 3 +++
1 file
On Fri, 2014-11-07 at 20:46 +0100, Hans de Goede wrote:
From: Oliver Schinagl oli...@schinagl.nl
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very
On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
From: Oliver Schinagl oli...@schinagl.nl
The A31 uses the AXP221 pmic for various voltages.
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
+ cfg |= 1 7;
+ cfg |= 1 3;
+
On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).
Also add some extra clock register constant defines.
Signed-off-by: Hans de Goede hdego...@redhat.com
On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
In preparation for adding sun6i dram support.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
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On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
Not used atm, for future use (e.g. PSCI).
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
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Hi,
On 11/08/2014 11:14 AM, Ian Campbell wrote:
On Fri, 2014-11-07 at 20:46 +0100, Hans de Goede wrote:
From: Oliver Schinagl oli...@schinagl.nl
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
Add full support for dram initialization, using a fixed clock and
autodetection
of the memory organization (numbers of channels, bus-width, etc.).
This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended
On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
Enable the SPL now that we've all the necessary bits in place.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
___
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On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.
Signed-off-by: Hans de Goede hdego...@redhat.com
Urk. Have Allwinner been prodded?
Acked-by: Ian Campbell
On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
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On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
Add proper Kconfig options to select the usb Vbus gpio-s, besides moving to
Kconfig being the right thing to do, an added advantage of this is that it
allows for boards without Vbus gpio-s.
Signed-off-by: Hans de Goede
On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
Add support for the 2 ehci controllers found on the sun6i (A31) soc.
Signed-off-by: Hans de Goede hdego...@redhat.com
You should probably run this by the usb custodian (Marek?) but for my
part:
Acked-by: Ian Campbell i...@hellion.org.uk
Hi,
Thanks for all the reviews!
On 11/08/2014 11:25 AM, Ian Campbell wrote:
On Fri, 2014-11-07 at 20:47 +0100, Hans de Goede wrote:
Add full support for dram initialization, using a fixed clock and
autodetection
of the memory organization (numbers of channels, bus-width, etc.).
This is
On Saturday, November 08, 2014 at 07:02:14 AM, Soeren Moch wrote:
Skip enclosure service devices when probing for usb storage devices.
This avoids long timeouts when probing for external usb harddisks
which provide Enclosure Services.
Signed-off-by: Soeren Moch sm...@web.de
I tweaked the
On Friday, November 07, 2014 at 04:53:48 PM, Rene Griessl wrote:
This patch adds driver support for the ASIX AX88179 USB3.0 to GbE network
adapter.
Driver has been tested on the RECS5250 COM module (similar to ARDALE5250).
Testcase was DHCP and PXE boot.
Signed-off-by: Rene Griessl
On Saturday, November 08, 2014 at 05:07:21 AM, Peng Fan wrote:
在 11/7/2014 8:17 PM, Marek Vasut 写道:
On Friday, November 07, 2014 at 12:45:51 PM, Peng Fan wrote:
在 11/7/2014 7:09 PM, Marek Vasut 写道:
On Friday, November 07, 2014 at 12:03:30 PM, Peng Fan wrote:
[...]
@@ -160,7 +174,7
On 07.11.2014 20:56, Dinh Nguyen wrote:
+CC: Graham Moore
On 11/07/2014 09:26 AM, Stefan Roese wrote:
Hi Dinh, Hi Vince!
snip
Could we not just use a plain GPL (v2) license here as well. Especially
since the other files in this driver are just normal GPL files.
Comments welcome.
Graham
Skip enclosure service devices when probing for usb storage devices.
This avoids long timeouts when probing for external usb harddisks
which provide Enclosure Services.
Signed-off-by: Soeren Moch sm...@web.de
Is it possible to provide a configuration option and some default
On Fri, Nov 7, 2014 at 8:12 PM, John Tobias john.tobias...@gmail.com wrote:
add SUPPORT_SPL for iMX6 SabreSD by default
This should be the last patch from the serie or it will break bisect.
--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br
On Fri, Nov 7, 2014 at 8:12 PM, John Tobias john.tobias...@gmail.com wrote:
This file will enable the support for SPL on iMX6 Sabrex families.
It tested on SD2 and SD3 mmc port.
This needs to be included before we actually use it. So before the
makefile inclusion. In fact I see no reason to
Hi Simon,
On Fri, Nov 7, 2014 at 10:22 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 4 November 2014 07:58, Bin Meng bmeng...@gmail.com wrote:
Currently only basic CPU information (x86 or x86_64) is displayed
on boot. This commit adds more detailed information output including
CPU
Hi Simon,
On Fri, Nov 7, 2014 at 10:23 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 6 November 2014 19:22, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 4 November 2014 07:58, Bin Meng bmeng...@gmail.com wrote:
Currently only basic CPU information (x86 or x86_64) is displayed
on
Thanks for the info.
I got a 2nd revision and will send it later.
Regards,
john
On Sat, Nov 8, 2014 at 5:13 AM, Otavio Salvador ota...@ossystems.com.br wrote:
On Fri, Nov 7, 2014 at 8:12 PM, John Tobias john.tobias...@gmail.com wrote:
This file will enable the support for SPL on iMX6 Sabrex
Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is needed for deepsleep.
Signed-off-by: Jeffrey Ladouceur jeffrey.ladouc...@freescale.com
---
The following dependent patches should be applied first:
Hi Bin,
On 8 November 2014 08:18, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 10:22 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 4 November 2014 07:58, Bin Meng bmeng...@gmail.com wrote:
Currently only basic CPU information (x86 or x86_64) is displayed
on
On 10 October 2014 08:21, Simon Glass s...@chromium.org wrote:
These functions really don't belong in physmem as they relate to the
cpu. Move them.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/cpu.c | 35 +++
On 10 October 2014 08:21, Simon Glass s...@chromium.org wrote:
Update this file to include x86_64 fields.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/include/asm/msr-index.h | 108
++-
1 file changed, 106 insertions(+), 2 deletions(-)
On 10 October 2014 08:21, Simon Glass s...@chromium.org wrote:
Display the type of CPU (x86 or x86_64) when starting up.
Signed-off-by: Simon Glass s...@chromium.org
Applied to u-boot-x86 and now in mainline.
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On 10 October 2014 08:21, Simon Glass s...@chromium.org wrote:
Add code to jump to a 64-bit Linux kernel. We need to set up a flat page
table structure, a new GDT and then go through a few hoops in the right
order.
Signed-off-by: Simon Glass s...@chromium.org
Applied to u-boot-x86 and now in
On 10 October 2014 08:21, Simon Glass s...@chromium.org wrote:
The boot_zimage() function is badly named it can also boot a raw kernel.
Rename it, and try to avoid pointers for memory addresses as it involves
lots of casting.
Signed-off-by: Simon Glass s...@chromium.org
---
On 10 October 2014 08:21, Simon Glass s...@chromium.org wrote:
We should use puts() instead of printf() where possible. Also clarify
the setup.bin message.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/lib/bootm.c | 2 +-
arch/x86/lib/zimage.c | 4 ++--
2 files changed, 3
On 10 October 2014 08:21, Simon Glass s...@chromium.org wrote:
Detect an x86_64 kernel and boot it in 64-bit mode.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/lib/bootm.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
Applied to u-boot-x86 and now in
On 10 October 2014 08:22, Simon Glass s...@chromium.org wrote:
The code density of x86_64 is not wonderful. Increase the maximum boot
size and adjust the load address to cope.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/coreboot.h | 3 ++-
1 file changed, 2
On 10 October 2014 08:21, Simon Glass s...@chromium.org wrote:
This is a bit odd in that we are permitted to boot images for either, even
though they are separate architectures.
Signed-off-by: Simon Glass s...@chromium.org
Applied to u-boot-x86 and now in mainline.
On 6 November 2014 19:57, Bin Meng bmeng...@gmail.com wrote:
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
This allows a board to do very early init, but no boards need to do this.
We may as well drop this feature.
Signed-off-by: Simon Glass s...@chromium.org
---
On 6 November 2014 19:55, Bin Meng bmeng...@gmail.com wrote:
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
This was missed when the real mode support was dropped. Remove it.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/config.mk | 1 -
1 file changed, 1
On 6 November 2014 20:49, Bin Meng bmeng...@gmail.com wrote:
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
We should invalidate the TLB right at the start to ensure that we don't get
false address translations even though paging is disabled.
Signed-off-by: Simon Glass
On 7 November 2014 02:37, Bin Meng bmeng...@gmail.com wrote:
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
This code is a little muddled, so tidy it up. Make sure that we put the
GDT in the right place and set it up properly.
Signed-off-by: Simon Glass s...@chromium.org
On 7 November 2014 02:49, Bin Meng bmeng...@gmail.com wrote:
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one
for this purpose. Also remove a useless/misleading comment.
Signed-off-by: Simon Glass
On 7 November 2014 03:21, Bin Meng bmeng...@gmail.com wrote:
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
The built in self test value is available in register eax on start-up. Save
it so that it can be accessed later. Unfortunately we must wait until the
global_data is
On 7 November 2014 03:07, Bin Meng bmeng...@gmail.com wrote:
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Some functions are missing prototypes. Fix those that are specific to x86.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/coreboot/coreboot.c |
On 7 November 2014 02:42, Bin Meng bmeng...@gmail.com wrote:
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Instead of having an x86-specific DRAM init function, adjust things so we
can use the normal one.
Signed-off-by: Simon Glass s...@chromium.org
---
This patch is for SPL support for iMX6 SabreSD. The said
patches has been tested to work on SD2 and SD3 port of the
said board.
After applying the following patches, it will produces
SPL and u-boot.img binary images. You should run the
two commands below to store it in your SD or eMMC.
sudo dd
To avoid compilation warning it need to define it in the header file.
---
include/mmc.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/mmc.h b/include/mmc.h
index d74a190..1d48bba 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -388,7 +388,9 @@ int
add the spl on build configuration of iMX6 SabreSD
---
include/configs/mx6sabresd.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 938030d..4d2e54a 100644
--- a/include/configs/mx6sabresd.h
+++
Add to call spl_board_mmc_init when CONFIG_SPL_MMC_SUPPORT is defined,
by default the mmc_initialize function will call board_mmc_init. But,
the said function is not link to the spl image.
---
drivers/mmc/mmc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
iMX6 SabreSD has different stack address compare
to the default stack address defined on the file.
The CONFIG_SYS_TEXT_BASE is defined in mx6sabre_common.h which is
same address defined on file. At the same time to avoid compilation
warnings.
---
include/configs/imx6_spl.h | 4
1 file
add SUPPORT_SPL for iMX6 SabreSD by default
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22eb2d5..ab0d284 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -609,6 +609,7 @@ config TARGET_MX6QSABREAUTO
config
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port.
---
board/freescale/mx6sabresd/mx6sabresd.c | 216
1 file changed, 216 insertions(+)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
This file is the default DCD configuration file for SPL
---
board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 54 +++
1 file changed, 54 insertions(+)
create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg
diff --git
add the spl on build configuration of iMX6 SabreSD
---
configs/mx6qsabresd_defconfig | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 67c1b77..14c80cc 100644
--- a/configs/mx6qsabresd_defconfig
+++
Changelog:
v4:
* Switch board_mmc_power_init to void since there is no return value check
* Add dev_index to twl4030_power_mmc_init, common ramp-up delay
* twl4030_power_mmc_init call with the relevant dev_index on boards
* No check against CONFIG_TWL4030_POWER (an obvious linker error is better
Not every device has multiple MMC slots available, so it makes sense to enable
only the required LDOs for the available slots. Generic code in omap_hsmmc will
enable both VMMC1 and VMMC2, in doubt.
Signed-off-by: Paul Kocialkowski cont...@paulk.fr
---
drivers/mmc/omap_hsmmc.c | 4 ++--
Some devices may use non-standard combinations of regulators to power MMC:
this allows these devices to provide a board-specific MMC power init function
to set everything up in their own way.
Signed-off-by: Paul Kocialkowski cont...@paulk.fr
---
drivers/mmc/mmc.c | 7 +++
include/mmc.h |
Boards using the TWL4030 regulator may not all use the LDOs the same way
(e.g. MMC2 power can be controlled by another LDO than VMMC2).
This delegates TWL4030 MMC power initializations to board-specific functions,
that may still call twl4030_power_mmc_init for the default behavior.
Signed-off-by:
Hello John,
On 08-11-14 19:22, John Tobias wrote:
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port.
---
snip
board/freescale/mx6sabresd/mx6sabresd.c | 216
1 file changed, 216 insertions(+)
diff --git
Le samedi 08 novembre 2014 à 20:55 +0100, Paul Kocialkowski a écrit :
Boards using the TWL4030 regulator may not all use the LDOs the same way
(e.g. MMC2 power can be controlled by another LDO than VMMC2).
This delegates TWL4030 MMC power initializations to board-specific functions,
that may
Raw images of U-Boot can be stored inside MMC partitions, so it makes sense to
read the partition table, looking for a partition number instead of using
a fixed sector address.
Signed-off-by: Paul Kocialkowski cont...@paulk.fr
---
README |4
common/spl/spl_mmc.c | 26
CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION ought to be called
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION to keep it consistent with other config
options such as: CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR.
In addition, it is not related to raw mode booting but to fs mode instead.
Signed-off-by: Paul Kocialkowski
This is a first attempt at adding support for U-Boot image load from raw
partitions. It does not support OS boot as I cannot test it on my current
setup.
This is going to be useful for the Optimus Black port (please do not consider
this as dead code because no board is using it right now, there
Hi Jeroen,
Thanks for the info. and you are correct. I have version 3 already...
Will send the v3 in a moment...
Regards,
john
On Sat, Nov 8, 2014 at 1:18 PM, Jeroen Hofstee jer...@myspectrum.nl wrote:
Hello John,
On 08-11-14 19:22, John Tobias wrote:
This patch will enable the support
Hello Paul,
On Sat, 8 Nov 2014 23:14:54 +0100, Paul Kocialkowski
cont...@paulk.fr wrote:
This is a first attempt at adding support for U-Boot image load from raw
partitions. It does not support OS boot as I cannot test it on my current
setup.
This is going to be useful for the Optimus
Le samedi 08 novembre 2014 à 23:19 +0100, Albert ARIBAUD a écrit :
Hello Paul,
On Sat, 8 Nov 2014 23:14:54 +0100, Paul Kocialkowski
cont...@paulk.fr wrote:
This is a first attempt at adding support for U-Boot image load from raw
partitions. It does not support OS boot as I cannot test it
To avoid compilation warning it need to define it in the header file.
---
include/mmc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/mmc.h b/include/mmc.h
index d74a190..37119b8 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -388,6 +388,9 @@ int mmc_legacy_init(int verbose);
This patch is for SPL support for iMX6 SabreSD. The said
patches has been tested to work on SD2 and SD3 port of the
said board.
After applying the following patches, it will produces
SPL and u-boot.img binary images. You should run the
two commands below to store it in your SD or eMMC.
sudo dd
Add to call spl_board_mmc_init when CONFIG_SPL_MMC_SUPPORT is defined,
by default the mmc_initialize function will call board_mmc_init. But,
the said function is not link to the spl image.
---
drivers/mmc/mmc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git
iMX6 SabreSD has different stack address compare
to the default stack address defined on the file.
The CONFIG_SYS_TEXT_BASE is defined in mx6sabre_common.h which is
same address defined on file. At the same time to avoid compilation
warnings.
---
include/configs/imx6_spl.h | 4
1 file
add the spl on include header file of iMX6 SabreSD
---
include/configs/mx6sabresd.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 938030d..4d2e54a 100644
--- a/include/configs/mx6sabresd.h
+++
add SUPPORT_SPL for iMX6 SabreSD by default
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22eb2d5..ab0d284 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -609,6 +609,7 @@ config TARGET_MX6QSABREAUTO
config
This file is the default DCD configuration file for SPL
---
board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 54 +++
1 file changed, 54 insertions(+)
create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg
diff --git
add the spl on build configuration of iMX6 SabreSD
---
configs/mx6qsabresd_defconfig | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 67c1b77..14c80cc 100644
--- a/configs/mx6qsabresd_defconfig
+++
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port.
---
board/freescale/mx6sabresd/mx6sabresd.c | 211 +++-
1 file changed, 209 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
Hello Paul,
On Sat, 08 Nov 2014 23:23:04 +0100, Paul Kocialkowski
cont...@paulk.fr wrote:
Le samedi 08 novembre 2014 à 23:19 +0100, Albert ARIBAUD a écrit :
Hello Paul,
On Sat, 8 Nov 2014 23:14:54 +0100, Paul Kocialkowski
cont...@paulk.fr wrote:
This is a first attempt at adding
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