Hi Stefan,
On 26 January 2015 at 06:17, Stefan Roese s...@denx.de wrote:
On 15.12.2014 15:19, Simon Glass wrote:
Enable CONFIG_OF_CONTROL so that U-Boot on these three boards uses a
device
tree for its configuration.
Signed-off-by: Simon Glass s...@chromium.org
This need further work on
Hi Marek,
On Monday, January 26, 2015 at 09:38:28 AM, Lukasz Majewski wrote:
Hi Marek,
Hi!
[...]
No, unless there's a convincing technical argument that the
currently mainline DWC2 gadget driver (the s3c one) can
absolutelly not be used for the broadcom SoC, I want to avoid
Hi,
On 25 January 2015 at 20:44, haikun.w...@freescale.com
haikun.w...@freescale.com wrote:
Hi,
My driver should support ls1021aqds, ls1021atwr, mcf5445x, mcf5227x, mcf52x2.
Please avoid top-posting.
The first one at least supports generic board. It doesn't look like
mcf5445x does though, so
Hi Stefan,
On 26 January 2015 at 02:35, Stefan Roese s...@denx.de wrote:
On 26.01.2015 10:23, Stefan Roese wrote:
diff --git a/board/amcc/canyonlands/Kconfig
b/board/amcc/canyonlands/Kconfig
index 0fc6877..cbc5ff9 100644
--- a/board/amcc/canyonlands/Kconfig
+++
Dear Simon,
In message 1422279795-3052-1-git-send-email-...@chromium.org you wrote:
From: Martin Dorwig dor...@tetronik.com
this is an atempt to make the export of functions typesafe.
I replaced the jumptable void ** by a struct (jt_funcs) with function
pointers.
The EXPORT_FUNC macro now
Hi,
On 25-01-15 16:24, Adam Sampson wrote:
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers;
it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro
USB socket for OTG and another for power in, HDMI, SATA, 5V power for
SATA devices, gigabit Ethernet, an IR
On Fri, Jan 23, 2015 at 4:40 PM, Steve Rae s...@broadcom.com wrote:
On 15-01-23 09:38 AM, Rob Herring wrote:
On Fri, Dec 12, 2014 at 5:51 PM, Steve Rae s...@broadcom.com wrote:
Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR
On 15.12.2014 15:19, Simon Glass wrote:
Enable CONFIG_OF_CONTROL so that U-Boot on these three boards uses a device
tree for its configuration.
Signed-off-by: Simon Glass s...@chromium.org
This need further work on the ppc4xx platforms to get it booting from
flash. As now the dtb is appended
Hi Ruchika,
On 26 January 2015 at 06:39, Simon Glass s...@chromium.org wrote:
Hi Ruchika,
On 23 January 2015 at 03:31, Ruchika Gupta ruchika.gu...@freescale.com
wrote:
Add a new rsa uclass for performing modular exponentiation and implement
the software driver basing on this uclass.
Otherwise this symbol will not be created in the .config.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Simon Glass s...@chromium.org
---
board/amcc/canyonlands/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig
index
This is necessary, as ppc4xx has the reset vector located at the end
of the U-Boot image. This needs to be flashed to the end of the NOR
flash. Adding the dtb to the main U-Boot image will break booting
on ppc4xx. This patch now embeds the dtb in the U-Boot image instead.
Signed-off-by: Stefan
This also displays the Board: line in the bootup text with the
generic board support code.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Simon Glass s...@chromium.org
---
board/amcc/canyonlands/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/board/amcc/canyonlands/Kconfig
These additional nodes need to be provided to get U-Boot to boot correctly
on the Canyonlands / Glacier board:
- chosen path to the console-uart
- reg-shift set to 0 in the uart device nodes
Signed-off-by: Stefan Roese s...@denx.de
Cc: Simon Glass s...@chromium.org
---
From: Martin Dorwig dor...@tetronik.com
this is an atempt to make the export of functions typesafe.
I replaced the jumptable void ** by a struct (jt_funcs) with function pointers.
The EXPORT_FUNC macro now has 3 fixed parameters and one
variadic parameter
The first is the name of the exported
On 23 January 2015 at 03:31, Ruchika Gupta ruchika.gu...@freescale.com wrote:
Public exponentiation which is required in rsa verify functionality is
tightly integrated with verification code in rsa_verify.c. The patch
splits the file into twp separating the modular exponentiation.
1.
Hi Simon,
On 26.01.2015 14:33, Simon Glass wrote:
Hmmm. This does not seem to work. With your patch series applied on
current top-of-tree I get this error (for glacier_ramboot or
canyonlands):
$ make -s -j10
board/amcc/canyonlands/Kconfig:38:warning: config symbol defined without
type
Hi Peng,
On 24 January 2015 at 07:34, Peng Fan b51...@freescale.com wrote:
Hi Simon,
On 1/23/2015 5:26 AM, Simon Glass wrote:
Hi Peng,
On 21 January 2015 at 04:09, Peng Fan peng@freescale.com wrote:
This patch add DT support for mxc gpio driver.
There are one place using
Dear Masahiro Yamada,
On 01/25/2015 07:11 AM, Masahiro Yamada wrote:
This commit moves source files as follows:
arch/arm/cpu/arm920t/at91/* - arch/arm/mach-at91/arm920t/*
arch/arm/cpu/arm926ejs/at91/* - arch/arm/mach-at91/arm926ejs/*
arch/arm/cpu/armv7/at91/* -
On 25.01.2015 07:11, Masahiro Yamada wrote:
Move
arch/arm/cpu/arm926ejs/kirkwood/* - arch/arm/mach-kirkwood/*
Note:
Perhaps, can we merge arch/arm/mach-kirkwood and
arch/arm/mvebu-common into arch/arm/mach-mvebu, like Linux?
Yes. This might need a bit work but definitely should be done.
On 01/25/2015 07:11 AM, Masahiro Yamada wrote:
The board select menu in arch/arm/Kconfig is still big.
To slim down it, this commit moves AT91 boards to
arch/arm/mach-at91/Kconfig.
Also, consolidate config SYS_SOC in each board Kconfig.
The Kconfig files under board/ directory were modified
Dear u-boot developers,
I'm looking for support of 1-wire protocol in this bootloader, without
luck up until now
I already search list archive with gmane and found only this old reference
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/117292
I also found some board implementation,
Signed-off-by: Alexander Merkle alexander.mer...@lauterbach.com
---
drivers/serial/arm_dcc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c
index 5dfb02f..e37 100644
--- a/drivers/serial/arm_dcc.c
+++
arm_dcc.c supported ARMv4 (ARM7) to ARMv6 (ARM11) correctly. All recent
CortexA/ARMv7 based cores share the mrc/mcr coprocessor calls of ARMv6.
Due to the missing #ifdef the ARM7/ARMv4 calls are used as soon as
CONFIG_CPU_V7 is defined. This results in an undefined instruction exception.
Hi Simon,
On Mon, Jan 26, 2015 at 9:31 PM, Simon Glass s...@chromium.org wrote:
Hi Stefan,
On 26 January 2015 at 06:17, Stefan Roese s...@denx.de wrote:
On 15.12.2014 15:19, Simon Glass wrote:
Enable CONFIG_OF_CONTROL so that U-Boot on these three boards uses a
device
tree for its
On 23 January 2015 at 03:31, Ruchika Gupta ruchika.gu...@freescale.com wrote:
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v6:
Fixed compilation error in this file for tools when FIT_SIGNATURE not enabled
Changes in v5:
New patch
On 23 January 2015 at 03:31, Ruchika Gupta ruchika.gu...@freescale.com wrote:
Currently the hash functions used in RSA are called directly from the sha1
and sha256 libraries. Change the RSA checksum library to use the progressive
hash API's registered with struct hash_algo. This will allow the
On 23 January 2015 at 03:31, Ruchika Gupta ruchika.gu...@freescale.com wrote:
Modify rsa_verify to use the rsa driver of DM library .The tools
will continue to use the same RSA sw library.
CONFIG_RSA is now dependent on CONFIG_DM. All configurations which
enable FIT based signatures have been
On 23 January 2015 at 03:31, Ruchika Gupta ruchika.gu...@freescale.com wrote:
Kconfig option added for devices which support RSA Verification.
1. RSA_SOFTWARE_EXP
Enables driver for supporting RSA Modular Exponentiation in Software
2. RSA_FREESCALE_EXP
Enables driver for supporting RSA
On 23 January 2015 at 03:31, Ruchika Gupta ruchika.gu...@freescale.com wrote:
Driver added for RSA Modular Exponentiation using Freescale Hardware
Accelerator CAAM. The driver uses UCLASS_MOD_EXP
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
---
Hi Ruchika,
On 23 January 2015 at 03:31, Ruchika Gupta ruchika.gu...@freescale.com wrote:
Add a new rsa uclass for performing modular exponentiation and implement
the software driver basing on this uclass.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass
On 23 January 2015 at 03:31, Ruchika Gupta ruchika.gu...@freescale.com wrote:
The hash_algo structure has some implementations in which progressive hash
API's are not defined. These are basically the hardware based implementations
of SHA. An API is added to find the algo which has progressive
The mips32 mips64 cache initialization code differs only in that the
mips32 code supports reading the cache size from coprocessor 0 registers
at runtime. Move the more developed mips32 version to a common
arch/mips/lib/cache_init.S remove the now-redundant mips64 version in
order to reduce
On Fri, Jan 23, 2015 at 09:54:12AM +0100, Hans de Goede wrote:
Hi,
On 22-01-15 22:03, Tom Rini wrote:
On Thu, Jan 22, 2015 at 08:10:06PM +0100, Hans de Goede wrote:
Hi,
On 22-01-15 17:20, Tom Rini wrote:
On Wed, Jan 21, 2015 at 09:03:25PM +0100, Hans de Goede wrote:
On some SoCs /
This series cleans up the MIPS cache code somewhat, and unifies the
mips32 mips64 implementations of it. This is largely in preparation
for further patches adding L2 cache support. The final patch of this
series fixes a bug encountered with recent cores on Malta boards.
Paul Burton (8):
MIPS:
As a step towards unifying the cache maintenance code for mips32
mips64 CPUs, stop using .set ISA directives in the more developed
mips32 version of the code. Instead, when present make use of the GCC
builtin for emitting a cache instruction. When not present, simply don't
bother with the .set
Move the more developed mips32 version of the cache maintenance
functions to a common arch/mips/lib/cache.c, in order to reduce
duplication between mips32 mips64.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
Cc: Daniel Schwierzeck daniel.schwierz...@gmail.com
---
arch/mips/cpu/mips32/cpu.c
Date: Mon, 26 Jan 2015 08:35:51 +0200
From: matti kaasinen matti.kaasi...@gmail.com
To: u-boot@lists.denx.de u-boot@lists.denx.de
Subject: [U-Boot] usb flash boot on am335x machines
Message-ID:
cadnuhn33oo-vguofkoq0-7r0dztaohboocrx2qzsa9lt1sv...@mail.gmail.com
Content-Type:
On 01/21/2015 11:21 PM, Minghuan Lian wrote:
Fix this:
warning: cast from pointer to integer of different size
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
drivers/net/e1000.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff
Hi Stefan,
On 26 January 2015 at 06:35, Stefan Roese s...@denx.de wrote:
Otherwise this symbol will not be created in the .config.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Simon Glass s...@chromium.org
---
board/amcc/canyonlands/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff
On 26 January 2015 at 06:35, Stefan Roese s...@denx.de wrote:
This is necessary, as ppc4xx has the reset vector located at the end
of the U-Boot image. This needs to be flashed to the end of the NOR
flash. Adding the dtb to the main U-Boot image will break booting
on ppc4xx. This patch now
Hi Hans,
On 26 January 2015 at 00:44, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 26-01-15 04:30, Simon Glass wrote:
Hi Adam,
On 25 January 2015 at 08:24, Adam Sampson a...@offog.org wrote:
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers;
it features 1G RAM,
Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and
Hello Simon,
On 01/26/2015 04:21 PM, Przemyslaw Marczak wrote:
This patchset adds support to driver model i2c api for Exynos i2c driver.
Few boards are using this driver, but the board peripherals are not ported
to the new api yet. So the CONFIG_DM_I2C_COMPAT is enabled.
Switch to dm i2c is
The gpt command always reports success even if writing the partition table
failed. Propagate the return value of gpt_restore so we get proper status
reported.
Signed-off-by: Rob Herring r...@kernel.org
---
common/cmd_gpt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On 26 January 2015 at 06:35, Stefan Roese s...@denx.de wrote:
This also displays the Board: line in the bootup text with the
generic board support code.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Simon Glass s...@chromium.org
---
board/amcc/canyonlands/Kconfig | 4
1 file changed,
On 26 January 2015 at 06:35, Stefan Roese s...@denx.de wrote:
These additional nodes need to be provided to get U-Boot to boot correctly
on the Canyonlands / Glacier board:
- chosen path to the console-uart
- reg-shift set to 0 in the uart device nodes
Signed-off-by: Stefan Roese
This patchset adds support to driver model i2c api for Exynos i2c driver.
Few boards are using this driver, but the board peripherals are not ported
to the new api yet. So the CONFIG_DM_I2C_COMPAT is enabled.
Switch to dm i2c is currentlly not possible for the few devices like
Trats2, Universal
This PMIC is not common for all Exynos5250
based boards, so should be romoved from
common config.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Minkyu Kang mk7.k...@samsung.com
---
include/configs/exynos5250-common.h | 3 ---
1 file changed, 3
There is no MAX77686 pmic on this board,
so the driver support should be removed.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
include/configs/arndale.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/configs/arndale.h
Without this alias setting, the seq numbers
of the i2c devices are wrong.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Minkyu Kang mk7.k...@samsung.com
---
arch/arm/dts/exynos5250-arndale.dts | 8
1 file changed, 8 insertions(+)
diff
Some versions of Exynos5 supports High-Speed I2C,
on few interfaces, this change allows support this.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Akshay Saraswat aksha...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
On 23 Jan 2015, mon...@monstr.eu wrote:
On 01/23/2015 02:05 AM, Tom Rini wrote:
I can't find a toolchain that doesn't give me something like: arm: +
zynq_zc70x +(zynq_zc70x) arch/arm/cpu/armv7/zynq/lowlevel_init.S:
Assembler messages: +(zynq_zc70x)
This commit adjusts the s3c24x0 driver to new i2c api
based on driver-model. The driver supports standard
and high-speed i2c as previous.
Tested on Trats2, Odroid U3, Arndale, Odroid XU3
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Heiko Schocher
This patch enables CONFIG_DM_I2C and also CONFIG_DM_I2C_COMPAT.
The last one should be removed when all the i2c peripheral
drivers will use dm i2c framework.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Akshay Saraswat aksha...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc:
This change fixes i2c bus numbering for Odroid U3.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes v2:
- new patch
---
arch/arm/dts/exynos4412-odroid.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git
This commit enable support for the above driver,
which was disabled in common config.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Minkyu Kang mk7.k...@samsung.com
---
include/configs/smdk5250.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
This patch enables CONFIG_DM_I2C and also CONFIG_DM_I2C_COMPAT.
The last one should be removed when the dm pmic framework will
be finished.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes v2:
- new patch
---
board/samsung/odroid/odroid.c
This patch modify i2c nodes in exynos4.dtsi with:
- adding proper interrupts arrays for each i2c node,
which allows to decode periph id
- add reg address for each i2c node for i2c driver internal use
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Hi Wolfgang,
On 26 January 2015 at 07:45, Wolfgang Denk w...@denx.de wrote:
Dear Simon,
In message 1422279795-3052-1-git-send-email-...@chromium.org you wrote:
From: Martin Dorwig dor...@tetronik.com
this is an atempt to make the export of functions typesafe.
I replaced the jumptable void
Currently, an environment variable must be used to store the randomly
generated UUID for each partition. This is not necessary, so make storing
the UUID optional. Now passing uuid_disk and uuid are optional when random
UUIDs are enabled.
Signed-off-by: Rob Herring r...@kernel.org
---
On 26.01.2015 17:09, Simon Glass wrote:
On 26 January 2015 at 06:35, Stefan Roese s...@denx.de wrote:
This also displays the Board: line in the bootup text with the
generic board support code.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Simon Glass s...@chromium.org
---
Reduce duplication between reading the configuration of the L1 dcache
icache by performing both using a macro which calculates the appropriate
line cache sizes from the coprocessor 0 Config1 register.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
Cc: Daniel Schwierzeck
Hi Masahiro,
On 24 January 2015 at 23:11, Masahiro Yamada yamad...@jp.panasonic.com wrote:
This commit moves files as follows:
arch/arm/cpu/arm720t/tegra20/* - arch/arm/mach-tegra/tegra20/*
arch/arm/cpu/arm720t/tegra30/* - arch/arm/mach-tegra/tegra30/*
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 2.
Signed-off-by: Paul Burton
The mips_init_[id]cache functions are small only called once from a
single callsite. Inlining them allows mips_cache_reset to avoid having
to bother moving arguments around leaves it a leaf function which is
thus able to simply keep the return address live in the ra register
throughout,
Reduce duplication by performing loops through cache tags using an
assembler macro.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
Cc: Daniel Schwierzeck daniel.schwierz...@gmail.com
---
arch/mips/lib/cache_init.S | 30 +-
1 file changed, 13 insertions(+), 17
At present SPL uses a single stack, either CONFIG_SPL_STACK or
CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and
environment) require a lot of stack, some boards set CONFIG_SPL_STACK to
point into SDRAM. They then set up SDRAM very early, before board_init_f(),
so that the larger
Le lundi 26 janvier 2015 13:14:31 UTC+1, Adam Sampson a écrit :
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers;
it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro
USB socket for OTG and another for power in, HDMI, SATA, 5V power for
SATA devices,
Am Montag, 26. Januar 2015, 15:45:31 schrieb Wolfgang Denk:
Is this a 100% binary compatible change? If not, should we not also
increment XF_VERSION ?
Yes it is .
The function pointers declared in _export.h are in the same sequence as they
were before.
Regards
Martin
On 25 January 2015 at 08:26, Simon Glass s...@chromium.org wrote:
There is no point in running the tests if U-Boot cannot be built. Abort in
this case.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
test/dm/test-dm.sh | 9 +++--
1 file
On 25 January 2015 at 08:26, Simon Glass s...@chromium.org wrote:
The root device corresponds to the root device tree node, so set this up.
Also add a few notes to the documentation.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
On 25 January 2015 at 08:26, Simon Glass s...@chromium.org wrote:
Make the error handling more standard to make it easier to build on top of
it. Also correct a bug in the error path where there is no parent.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Masahiro Yamada
On 25 January 2015 at 08:26, Simon Glass s...@chromium.org wrote:
Mention that the devices are probed ready for use.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
include/dm/uclass.h | 4
1 file changed, 4 insertions(+)
Applied to
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
Allow parent drivers to be called when a new child is bound to them. This
allows a bus to set up information it needs for that child.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Masahiro Yamada
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
In many cases the child platform data for a device's children is defined by
the uclass rather than the individual devices. For example, a SPI bus needs
to know the chip select and speed for each of its children. It makes sense
On 25 January 2015 at 19:00, Masahiro Yamada yamad...@jp.panasonic.com wrote:
On Sun, 25 Jan 2015 08:27:06 -0700
Simon Glass s...@chromium.org wrote:
In many cases the per-child private data for a device's children is defined
by the uclass rather than the individual driver. For example, a
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
This is common to all SPI drivers and specifies a structure used by the
uclass. It makes more sense to define it in the uclass.
Reviewed-by: Masahiro Yamada yamad...@jp.panasonic.com
Signed-off-by: Simon Glass s...@chromium.org
Hi,
On 26-01-15 16:18, Tom Rini wrote:
On Fri, Jan 23, 2015 at 09:54:12AM +0100, Hans de Goede wrote:
Hi,
On 22-01-15 22:03, Tom Rini wrote:
On Thu, Jan 22, 2015 at 08:10:06PM +0100, Hans de Goede wrote:
Hi,
On 22-01-15 17:20, Tom Rini wrote:
On Wed, Jan 21, 2015 at 09:03:25PM +0100, Hans
On 25 January 2015 at 08:26, Simon Glass s...@chromium.org wrote:
Rather than assuming that the chip offset length is 1, allow it to be
provided. This allows chips that don't use the default offset length to
be used (at present they are only supported by the command line 'i2c'
command which
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
Now that we have new bus features, update README.txt and the SPI docs to
explain these.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- Drop RFC prefix since this series has been
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
This is no-longer needed since all platforms use SPI for cros_ec.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- Add patches to tidy up cros_ec using new I2C/SPI features
Hello everyone,
I have a Gumstix Overo (OMAP3) COM here that I am evaluating BCH8 ECC
scheme on boot-loader (2014.10) and the kernel (3.17.7).
Traditionally the board has been configured with 1 bit HAM, as are other
OMAP3 boards.
I have these changes in my board config:
+#define CONFIG_BCH
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
For buses, after a child is bound, allow the uclass to perform some
processing. This can be used to figure out the address of the child (e.g.
the chip select for SPI slaves) so that it is ready to be probed.
This avoids bus
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
At present we use struct spi_slave as our device pointer in a lot of places
to avoid changing the old SPI API. At some point this will go away.
But for now, it is better if the SPI uclass sets up this pointer, rather
than
Dear Simon,
In message CAPnjgZ1wzmspVjB8dqDJBZDu2Dpu+JLSS=cmaddpkhptyrh...@mail.gmail.com
you wrote:
Is this a 100% binary compatible change? If not, should we not also
increment XF_VERSION ?
If a board has move to driver model and doesn't use
CONFIG_DM_I2C_COMPAT (and this should
Hi Tom,
The following changes since commit 37b608a52dcb13312a4f7ccea199cd6bac76d298:
powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200
(2015-01-23 16:56:09 -0500)
are available in the git repository at:
http://git.denx.de/u-boot-x86.git
for you to fetch changes up to
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
At present we try to use the 'reg' property and device tree aliases to give
devices a sequence number. The 'reg' property is often actually a memory
address, so the sequence numbers thus-obtained are not useful. It would be
On 25 January 2015 at 18:58, Masahiro Yamada yamad...@jp.panasonic.com wrote:
On Sun, 25 Jan 2015 08:27:04 -0700
Simon Glass s...@chromium.org wrote:
This is useful to check which uclass a device is in.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Masahiro Yamada
On 25 January 2015 at 18:57, Masahiro Yamada yamad...@jp.panasonic.com wrote:
On Sun, 25 Jan 2015 08:27:00 -0700
Simon Glass s...@chromium.org wrote:
When using allocated platform data, allocate it when we bind the device.
This makes it possible to fill in this information before the device
On 25 January 2015 at 18:56, Masahiro Yamada yamad...@jp.panasonic.com wrote:
On Sun, 25 Jan 2015 08:27:01 -0700
Simon Glass s...@chromium.org wrote:
For buses it is common for parents to need to know the address of the child
on the bus, the bus speed to use for that child, and other
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
Update the driver model support, and remove the old code. Change snow to
use this new support.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- Add patches to tidy up cros_ec using new
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
I2C is now deprecated on ARM platforms and there are no devices that use it
with the v3 protocol. We can't require v3 support if we want to support I2C.
Adjust the error handling to suit.
Signed-off-by: Simon Glass
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
We don't want to bind devices which should never be used.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v3: None
Changes in v2:
- Add patches to tidy up
Hi Wolfgang,
On 26 January 2015 at 11:55, Wolfgang Denk w...@denx.de wrote:
Dear Simon,
In message
CAPnjgZ1wzmspVjB8dqDJBZDu2Dpu+JLSS=cmaddpkhptyrh...@mail.gmail.com you
wrote:
Is this a 100% binary compatible change? If not, should we not also
increment XF_VERSION ?
If a board has
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
Use a single exit point when we have an error and add debugging there.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/mtd/spi/sandbox.c | 7 +--
1 file changed, 5
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
Some buses need to set up their devices before they can be used. This setup
may well be common to all buses in a particular uclass. Support a common
pre-probe method for the uclass, called before any bus devices are probed.
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
At present we go through various contortions to store the SPI slave's chip
select in its private data. This only exists when the slave is active so
must be set up when it is probed. Until the device is probed we don't
actually
On 25 January 2015 at 08:27, Simon Glass s...@chromium.org wrote:
These have moved to driver model so we don't need the fdtdec support.
Signed-off-by: Simon Glass s...@chromium.org
Applied to -u-boot-dm
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On 25 January 2015 at 23:53, Minkyu Kang mk7.k...@samsung.com wrote:
On 26/01/15 00:27, Simon Glass wrote:
This has moved to driver model so we don't need the fdtdec support.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
include/fdtdec.h | 1 -
On 25 January 2015 at 19:05, Masahiro Yamada yamad...@jp.panasonic.com wrote:
On Sun, 25 Jan 2015 08:27:13 -0700
Simon Glass s...@chromium.org wrote:
At present we go through various contortions to store the I2C's chip
address in its private data. This only exists when the chip is active so
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