On 21/10/2019 08:32, Keerthy wrote:
On 15/10/19 12:27 PM, Lokesh Vutla wrote:
[..snip..]
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index f431f3bf29..605b52905e 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -31,6 +31,7 @@ enum uclass_id {
Add Pinctrl driver for MediaTek MT8518 SoC.
Signed-off-by: mingming lee
---
arch/arm/dts/mt8518.dtsi | 9 +-
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8518.c | 411
This adds a general board file based on MT8518 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
This commit is adding the basic boot support for the MT8518 eMMC board.
Signed-off-by: mingming lee
---
Changes for v2:
-
1.Support cmd response and data tuning together.
2.Support hs400 cmd responese tuning.
Signed-off-by: mingming lee
---
Changes for v2:
- add hs400 support
---
drivers/mmc/mtk-sd.c | 209 +++
1 file changed, 193 insertions(+), 16 deletions(-)
diff
Hi Priyanka,
> -Original Message-
> From: Priyanka Jain
> Sent: Monday, October 21, 2019 11:13 AM
> To: Wasim Khan ; Z.q. Hou
> Cc: u-boot@lists.denx.de
> Subject: RE: [PATCH 3/8] pci: layerscape: Update API names for layerscape
> fixup
>
>
> >-Original Message-
> >From:
This patch series add basic boot support on eMMC for the MediaTek
MT8518 SoC based boards. This series add the clock, pinctrl drivers
and the SoC initializaton code.
---
Changes for v2:
- fixed issues in v1: drop unused 'devices',delete no need code
and print debug log using debug()
-
Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee
---
Changes for v2:
-drop unused 'device' in dtsi to keep it simple
---
arch/arm/dts/mt8518.dtsi | 91 ++
On Mon, Oct 21, 2019 at 7:24 AM Simon Glass wrote:
>
> In TPL we try to minimise code size so do not include the PCI subsystem.
> We can use fixed BARs and drivers can directly program the devices that
> they need.
>
> However we do need to bind the devices on the PCI bus and without PCI this
>
On Fri, Oct 11, 2019 at 5:52 PM Ley Foon Tan wrote:
>
> This is 5th version of patchset to add Intel Agilex SoC[1] support.
> Most of changes are related to move CCU driver to DM, remove *_manager_s10.h
> and include *_manager_soc64.h directly. Detail changelog can find in
> commit message.
>
>
On Thu, Oct 10, 2019 at 3:37 PM Ley Foon Tan wrote:
>
> This is 4th version of patchset to convert reset, system and clock manager
> drivers to use #define instead of struct. This patchset get managers' base
> address from DT node instead of using #define.
>
> Patch 1 unchanged, patch 2,3,4
From: Tero Kristo
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.
Signed-off-by: Tero Kristo
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production.
Add support for Adaptive Voltage scaling class 0 support
for AM6 family of devices. Adaptive voltage scaling class 0
implies that optimized
> Since we move the ATF bl31 entry for 64bit CPUs to 0x4, we need to
> limit the SPL size in 0x4(start from 0) so that we don't need to do
> the relocate for ATF loading.
> Note that there will be separate BSS, STACK and MALLOC heap, so the size
> 0x4(256KB) should be enough for SPL
Hi,
On Thu, Aug 15, 2019 at 01:57:23PM +0530, Manivannan Sadhasivam wrote:
> Hello,
>
> This patchset adds initial board support for iMX8QXP AI_ML board
> from Einfochips. This board is one of the Consumer Edition and AI
> boards of the 96Boards family.
>
> This initial supports contains
> From: Jagan Teki
> Date: Mon, 21 Oct 2019 10:56:39 +0530
>
> Hi Kever,
>
> On Fri, Oct 18, 2019 at 4:26 PM Kever Yang wrote:
> >
> > Jagan,
> >
> >
> > On 2019/10/18 上午3:07, Jagan Teki wrote:
> > > idbloader.img name is specific to rockchip,
> >
> > This is specific for rockchip, like rksd,
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.
Add a new Kconfig option to permit this. Default it to 'y' so that
Add clock driver for MediaTek MT8518 SoC.
Signed-off-by: mingming lee
---
drivers/clk/mediatek/Makefile |1 +
drivers/clk/mediatek/clk-mt8518.c | 1558
include/dt-bindings/clock/mt8518-clk.h | 249
3 files changed, 1808 insertions(+)
create mode
On Mon, Oct 21, 2019 at 7:26 AM Simon Glass wrote:
>
> Add a simple command to show information about the PMC.
PMC is a part of almost all Intel Atom SoCs. Can you describe how can
it be utilized for example in case of Tangier?
--
With Best Regards,
Andy Shevchenko
On Mon, Oct 21, 2019 at 7:14 AM Simon Glass wrote:
>
> Adds a driver for the apollolake Primary-to-sideband bus. This supports
> various child devices. It supposed both device tree and of-platdata.
> +static int apl_p2sb_probe(struct udevice *dev)
> +{
> + if (spl_phase() == PHASE_TPL)
> +
On Mon, Oct 21, 2019 at 7:28 AM Simon Glass wrote:
>
> Add a driver for the apollolake UART. It uses the standard ns16550 device
> but also sets up the input clock with LPSS and supports configuration via
> of-platdata.
This must be generic driver. The LPSS block is the same for all Intel
SoCs
On Mon, Oct 21, 2019 at 6:53 AM Simon Glass wrote:
>
> Add very basic support for taking an lpss device out of reset.
> arch/x86/cpu/apollolake/lpss.c | 31 +++
Must be in intel_common.
--
With Best Regards,
Andy Shevchenko
On Mon, Oct 21, 2019 at 6:58 AM Simon Glass wrote:
>
> This driver models some sort of interrupt thingy but there are so many
> abreviations that I cannot find out what it stands for. Possibly something
> to do with interrupts.
From documentation.
Interrupt Timer Subsystem
The below code is
This patch-set is to clean up driver. There is still a lot of work
to clean up the driver, and patches will be sent in the future.
Yangbo Lu (3):
mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC
mmc: fsl_esdhc: remove redundant DM_MMC checking
mmc: fsl_esdhc: drop i.MX DDR support
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already
support it, so let's force to use it.
- Drop non-BLK support for DM_MMC introduced by below patch.
66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled
- Support only DM_MMC + BLK (assuming BLK is always enabled
A previous patch below adding DDR mode support was actually for i.MX
platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC,
it uses different process for DDR mode, and hasn't been supported.
Let's drop DDR support code for i.MX in fsl_esdhc driver.
0e1bf61 mmc: fsl_esdhc: Add
On Mon, Oct 21, 2019 at 7:02 AM Simon Glass wrote:
>
> Add a driver for the apollolake GPIOs. It also handles pinctrl since this
> is not very well separated on x86.
> arch/x86/cpu/apollolake/gpio.c| 735 ++
No, no. It must be a common for x86, starting from
On Mon, Oct 21, 2019 at 7:01 AM Simon Glass wrote:
>
> Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
> Add support for these along with suitable configuration options.
> +#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0)
Perhaps it would be useful to
Hi Miquel,
On Mon, Oct 21, 2019 at 1:38 PM Miquel Raynal wrote:
>
> Hi Jagan,
>
> Gentle ping.
>
> As discussed half a year ago, please do not trash this series :)
Please give us sometime, will update accordingly.
___
U-Boot mailing list
Hi Harald,
On 18/10/2019 11.29, Harald Seiler wrote:
> Hi Claudius,
>
> On Wed, 2019-10-16 at 15:27 +0200, Claudius Heine wrote:
>> The only register used in that function is gpr10, which is used to store
>> the flag. So naming it after this makes sense.
>
> I think the old name had a reason:
On Mon, Oct 21, 2019 at 11:41 AM Andy Shevchenko
wrote:
>
> On Mon, Oct 21, 2019 at 6:58 AM Simon Glass wrote:
> >
> > This driver models some sort of interrupt thingy but there are so many
> > abreviations that I cannot find out what it stands for. Possibly something
> > to do with interrupts.
From: Tero Kristo
Add VTM node for voltage and thermal management. For u-boot, this is needed
for supporting AVS class 0, as the efuse values for the OPPs are stored
under the VTM.
Signed-off-by: Tero Kristo
Signed-off-by: Keerthy
---
arch/arm/dts/k3-am65-wakeup.dtsi | 7 +++
1 file
Notify AVS driver upon setting clock rate so that voltage
is changed accordingly.
Signed-off-by: Keerthy
---
drivers/clk/clk-ti-sci.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/clk-ti-sci.c b/drivers/clk/clk-ti-sci.c
index c25415d410..478349f22f 100644
---
From: Tero Kristo
Link the vdd-supplies for the voltage domains under the VTM node. Also,
enable the node under SPL. This will enable the AVS class 0 support on
am65x-evm board.
Signed-off-by: Tero Kristo
Signed-off-by: Keerthy
---
arch/arm/dts/k3-am654-r5-base-board.dts | 6 ++
1 file
From: Tero Kristo
TPS62363 is used to control the MPU_VDD voltage, so enable the driver
for this.
Signed-off-by: Tero Kristo
Signed-off-by: Keerthy
---
configs/am65x_evm_r5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/am65x_evm_r5_defconfig
On 2019/10/21 下午6:06, Soeren Moch wrote:
> Since we move the ATF bl31 entry for 64bit CPUs to 0x4, we need to
> limit the SPL size in 0x4(start from 0) so that we don't need to do
> the relocate for ATF loading.
> Note that there will be separate BSS, STACK and MALLOC heap, so the size
Thanks, will send v2 soon.
On Wed, Oct 16, 2019 at 12:47 PM Igor Opaniuk wrote:
>
> Hi Sam,
>
> On Fri, Aug 9, 2019 at 3:38 PM Sam Protsenko
> wrote:
> >
> > Add optional parameter to 'avb verify' sub-command, so that user is able
> > to specify which slot to use, in case when user's
On Mon, Oct 21, 2019 at 6:32 AM Simon Glass wrote:
>
> Apollolake is an Intel SoC generation aimed at relatively low-end embedded
> systems. It was released in 2016 but has become more popular recently with
> some embedded boards using it.
>
> This series adds support for apollolake. As an
Hi Simon,
On Fri, Oct 18, 2019 at 12:38 AM Jagan Teki wrote:
>
> TPL-based rockchip platform like rk3288, rk3328, rk3368
> and rk3399 has three stage boot loaders like TPL, SPL and
> U-Boot proper. For each stage we need to burn the image
> on to flash with respective offsets.
>
> This patch
On Mon, Oct 21, 2019 at 7:29 AM Simon Glass wrote:
>
> This driver handles communication with the systemagent which needs to be
> told when U-Boot has completed its init.
> +#define VTBAR_MASK 0xfff000ull
Don't we have GENMASK() ?
--
With Best Regards,
Andy Shevchenko
On Mon, Oct 21, 2019 at 7:25 AM Simon Glass wrote:
>
> Add a driver for the apollolake power unit. It is modelled as a syscon
> driver since it only needs to be probed.
appollolake -> Appollo Lake (everywhere in the series)
power unit -> P-Unit (it's very known for Intel SoCs term, you may
Miss the SPI_FLASH_BAR for the ESPI controller of FSL.
Signed-off-by: Xiaowei Bao
---
drivers/spi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b8ca2bd..7003569 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -367,6
Remove redundant DM_MMC checking which is already in DM_MMC conditional
compile block.
Signed-off-by: Yangbo Lu
---
drivers/mmc/fsl_esdhc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 4eceec5..03c54c3 100644
---
Introduce the CONFIG_LDO_ENABLED_MODE option so that i.MX7ULP boards
designed to operate with LDO enabled mode can work with 0.95V at LDO
output in RUN mode as per the datasheet.
Signed-off-by: Fabio Estevam
---
arch/arm/mach-imx/mx7ulp/Kconfig | 5 +++
arch/arm/mach-imx/mx7ulp/soc.c | 58
The LDOVL definitions is common to all the modes, not only RUN mode,
so in order to avoid confusion, remove the _RUN notation from the PMC1
LDOVL definitions.
Signed-off-by: Fabio Estevam
---
arch/arm/mach-imx/mx7ulp/soc.c | 20 ++--
1 file changed, 10 insertions(+), 10
Correct the name of the define used CONFIG_IS_ENABLED which is
not aligned with Kconfig name: CONFIG_$(SPL_)PINCONF_RECURSIVE.
The recursive calls is conditional only for UCLASS_PINCONFIG
"pinconfig" driver.
It is always needed to call pinctrl_post_bind for UCLASS_PINCTRL
"pinctrl", the test
From: Igor Opaniuk
Add support for updating FCB/DBBT on i.MX7:
- additional new fields in FCB structure
- Leverage hardware BCH/randomizer for writing FCB
Signed-off-by: Igor Opaniuk
---
arch/arm/include/asm/mach-imx/imx-nandbcb.h | 12 ++
arch/arm/mach-imx/Kconfig | 2
From: Igor Opaniuk
Extend GPMI Integrated ECC Control Register Description, include
additional defines for enabling randomizer function and providing
proper randomizer type.
For additional details check i.MX7 APR, section
9.6.6.3 GPMI Integrated ECC Control Register Description
(GPMI_ECCCTRLn)
This introduces support for writing BCB(FCB/FDDT) for i.MX7 NAND-based
platforms and additional subcommand for writing BCB
only (without firmware).
v2:
- Switch to runtime detection of SoC(e.g. is_mx7()) instead of ifdeffery
- Fix build for imx6
Igor Opaniuk (5):
imx: gpmi: add defines for hw
Set gd->fb_base so it can be shown with bdinfo command.
Signed-off-by: Sébastien Szymanski
---
Changes for v3:
- use plat->base instead of fb_start
drivers/video/mxsfb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index
Migrate to DM_VIDEO, update the device tree and remove code that is no
longer necessary.
Reviewed-by: Peng Fan
Signed-off-by: Sébastien Szymanski
---
Changes for v2:
- added Reviewed-by tag
arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi | 10 ++
arch/arm/dts/imx6ul-opos6uldev.dts |
Migrate to DM_ETH and remove code that is no longer necessary.
Reviewed-by: Peng Fan
Signed-off-by: Sébastien Szymanski
---
Changes for v2:
- added Reviewed-by tag
arch/arm/mach-imx/mx6/opos6ul.c | 76 +++--
configs/opos6uldev_defconfig| 2 +
From: Igor Opaniuk
On i.MX7 in a sake of reducing the disturbances caused by a neighboring
cells in the FCB page in the NAND chip, a randomizer is enabled when
reading the FCB page by ROM bootloader.
Add API for setting BCH to specific layout (and restoring it back) used by
ROM bootloader to be
From: Igor Opaniuk
Move code for writing FCB/DBBT pages to a separate function
Signed-off-by: Igor Opaniuk
---
arch/arm/mach-imx/cmd_nandbcb.c | 221 ++--
1 file changed, 122 insertions(+), 99 deletions(-)
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c
As per the i.MX7ULP datasheet, it can boot in LDO enabled mode
or LDO bypass mode.
Print the LDO mode status in the U-Boot log for convenience.
Signed-off-by: Fabio Estevam
---
arch/arm/mach-imx/mx7ulp/soc.c | 20
1 file changed, 20 insertions(+)
diff --git
Remove the duplicated configs introduced when the same patch is
applied twice times:
- commit e878b53a79d1 ("dm: pinctrl: introduce PINCONF_RECURSIVE
option")
- commit c20851b3d850 ("dm: pinctrl: introduce PINCONF_RECURSIVE
option")
Signed-off-by: Patrick Delaunay
---
From: Fabio Estevam
Add an entry for the Adesto AT25SL321 SPI NOR chip.
This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board.
Signed-off-by: Fabio Estevam
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c
The Embedded Artists COM board is based on NXP i.MX7ULP.
It has a BD70528 PMIC from Rohm with discrete DCDC powering option and
improved current observability (compared to the existing NXP i.MX7ULP EVK).
Add the initial support for the board.
Signed-off-by: Fabio Estevam
---
From: Ye Li
The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
to work.
This patch only supports OTG0 with UTMI PHY.
By default the i.MX7ULP DDR frequency runs at 352 MHz, but not all
i.MX7ULP based systems are able to run at such frequency, such as
the i.MX7ULP Embedded Artists board.
Introduce a CONFIG_IMX7ULP_LOWER_DDR_FREQUENCY option that
allows running DDR at a lower frequency of 316.8MHz.
When such
scg_a7_apll_init() is not called anywhere, so remove such dead code
Signed-off-by: Fabio Estevam
---
arch/arm/include/asm/arch-mx7ulp/scg.h | 1 -
arch/arm/mach-imx/mx7ulp/scg.c | 61 --
2 files changed, 62 deletions(-)
diff --git
If a board defines a custom boot order using board_boot_order(), the
boot-device which is currently attempted might differ from the return
value of spl_boot_device(). Use the given boot_device parameter instead
of calling spl_boot_device() to prevent an incorrect "unsupported
device" error.
On 21.10.19 12:15, Kever Yang wrote:
>
>
> On 2019/10/21 下午6:06, Soeren Moch wrote:
>> > Since we move the ATF bl31 entry for 64bit CPUs to 0x4, we need to
>> > limit the SPL size in 0x4(start from 0) so that we don't need to do
>> > the relocate for ATF loading.
>> > Note that there
The FDT specification [0] gives a requirement of aligning properties on
32-bits. Make sure that the compiler is aware of this constraint when
accessing 64-bits properties.
[0]:
https://github.com/devicetree-org/devicetree-specification/blob/master/source/flattened-format.rst
Signed-off-by:
From: Igor Opaniuk
Add subcommand for add writing BCB only, where we provide appropriate
offsets for firmware1 and firmware2 and size.
Example of usage:
- nandbcb bcbonly 0x0018 0x0008 0x0020
Writing 1024 bytes to 0x0: randomizing
OK
Writing 1024 bytes to 0x2: randomizing
OK
Hi Sam,
On Mon, Oct 21, 2019 at 1:55 PM Sam Protsenko
wrote:
>
> Add optional parameter to 'avb verify' sub-command, so that user is able
> to specify which slot to use, in case when user's partitions are
> slotted. If that parameter is omitted, the behavior of 'avb verify' will
> be the same as
On Mon, 23 Sep 2019 at 10:39, Philippe Reynes
wrote:
>
> This commit enable the command aes on sandbox.
> Then, it may be used on pytest.
>
> Signed-off-by: Philippe Reynes
> ---
> configs/sandbox_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass
On Mon, 23 Sep 2019 at 10:48, Philippe Reynes
wrote:
>
> In the code, we use the size of the key for the
> size of the block. It's true when the key is 128 bits,
> but it become false for key of 192 bits and 256 bits.
> So to prepare the support of aes192 and 256,
> we introduce a constant for
From: Ye Li
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ,
so update the interface to add new argument.
Signed-off-by: Ye Li
---
arch/arm/include/asm/mach-imx/sys_proto.h | 3 ++-
arch/arm/mach-imx/imx_bootaux.c | 4 ++--
arch/arm/mach-imx/sip.c | 4
Hi Pierre-Jean,
On Mon, Oct 21, 2019 at 1:43 PM Pierre-Jean Texier wrote:
> On top-of master 32ded50 ("spl: mmc: make eMMC HW boot
> partition configuration optional ")
> I am not able to reproduce the described behavior.
I used u-boot-imx tree and this is what I get:
ls -al u-boot-dtb.imx
On 10/21/19 3:52 PM, Fabio Estevam wrote:
[...]
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 30c6b69be8..14ce98c778 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -142,7 +142,7 @@ config USB_EHCI_MX5
>
> config USB_EHCI_MX6
>
Booting with images in eMMC hardware boot partition doesn't work
because the container header is loaded from user partition, thus
the loaded data doesn't have a valid header. Add partition switching
to support booting from eMMC boot partitions.
Signed-off-by: Anatolij Gustschin
---
On Fri, 18 Oct 2019 at 14:53, Tom Rini wrote:
>
> In a number of our stanzas we had multi-line commands that were one
> space short of alignment, correct this.
>
> Signed-off-by: Tom Rini
> ---
> .gitlab-ci.yml | 40
> 1 file changed, 20 insertions(+),
On Thu, Aug 15, 2019 at 8:55 PM Sam Protsenko
wrote:
>
> Hi Eugeniu,
>
> On Tue, Aug 13, 2019 at 7:59 PM Eugeniu Rosca wrote:
> >
> > Hi Sam,
> >
> > On Fri, Aug 09, 2019 at 07:16:03PM +0300, Sam Protsenko wrote:
> > > The requested_partitions[] array should contain only boot partitions.
> > >
All platforms which are using MANUAL_RELOC are jumping back to origin
location when repeatable command is called. The reason is that cmd_rep link
is not updated properly. Issue can be reproduced by rewriting origin
U-Boot location through (for example) file download by tftp command.
Fixes:
On Mon, Oct 21, 2019 at 09:25:56AM -0600, Simon Glass wrote:
> Hi Tom,
>
> On Fri, 18 Oct 2019 at 14:53, Tom Rini wrote:
> >
> > From: Marek Vasut
> >
> > Fix the following spit from pytest:
> >
> > u-boot/test/py/conftest.py:438: RemovedInPytest4Warning: MarkInfo objects
> > are deprecated as
Borrow ID reading code from Ye Li (NXP U-Boot, commit ID 5b443e3e2617)
and add the commit IDs to the environment.
Signed-off-by: Anatolij Gustschin
---
arch/arm/mach-imx/imx8/misc.c | 61 ++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git
Add function for reading SECO-FW commit id.
Signed-off-by: Anatolij Gustschin
---
arch/arm/include/asm/arch-imx8/sci/sci.h | 1 +
drivers/misc/imx8/scu_api.c | 27
2 files changed, 28 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h
This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.
The port was straightforward:
- remove the interrupt handling and the completion by busy polling the
Also align the fspi node with the kernel one.
Signed-off-by: Michael Walle
---
arch/arm/dts/fsl-ls1028a.dtsi | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 43a154e8e7..774e477542 100644
---
Use tab instead of spaces.
Signed-off-by: Michal Simek
---
arch/microblaze/cpu/start.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 22903e3bc4e5..cbec299b7d8b 100644
--- a/arch/microblaze/cpu/start.S
+++
The default value of CONFIG_SYS_CBSIZE is too small when we need
to input long commands or when using long kernel command line.
The default value of CONFIG_SYS_MAXARGS is too small to add a long
command line, and the kernel might not boot as intended without the
complete bootargs. Increase
Hi Patrick,
On Mon, 21 Oct 2019 15:07:54 +0200
Patrick Delaunay patrick.delau...@st.com wrote:
> Remove the duplicated configs introduced when the same patch is
> applied twice times:
There is already a patch pending http://patchwork.ozlabs.org/patch/1179889
--
Anatolij
U-Boot binary has grown in such a way that it goes beyond the reserved
area for the environment variables.
Running "saveenv" followed by a "reset" causes U-Boot to hang because
of this overlap.
Fix this problem by increasing the CONFIG_ENV_OFFSET size.
Also, in order to prevent this
Hi Tom,
On Fri, 18 Oct 2019 at 14:53, Tom Rini wrote:
>
> We need to make sure that we prepend changes to PATH, so that any
> binaries we need to provide ourselves are used not overwrite PATH for
This reads a bit wonkily.
> this. Overwriting PATH like this breaks the python virtualenv PATH
>
Hi Tom,
On Fri, 18 Oct 2019 at 14:53, Tom Rini wrote:
>
> From: Marek Vasut
>
> Fix the following spit from pytest:
>
> u-boot/test/py/conftest.py:438: RemovedInPytest4Warning: MarkInfo objects are
> deprecated as they contain merged marks which are hard to deal with correctly.
> Please use
On Thu, 19 Sep 2019 at 07:40, Philippe Reynes
wrote:
>
> This commit enable the command aes on sandbox.
> Then, it may be used on pytest.
>
> Signed-off-by: Philippe Reynes
> ---
> configs/sandbox_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass
Hello Fabio,
Le 21/10/2019 à 16:22, Fabio Estevam a écrit :
U-Boot binary has grown in such a way that it goes beyond the reserved
area for the environment variables.
Running "saveenv" followed by a "reset" causes U-Boot to hang because
of this overlap.
On top-of master 32ded50 ("spl:
Hi Rayees,
On Sat, 19 Oct 2019 at 20:14, Rayees Shamsuddin
wrote:
>
> Simon,
>
> Thanks for all your great and pioneering effort on verified u-boot. I am
> benefiting a lot for your work. I am trying to implement verified u-boot on
> Tegra TX2.
>
> Based on the wonderful documentation that you
Record two bootstages and add "Starting kernel" message to have standard
handoff message between U-Boot and OS.
Also use debug() instead of #ifdef DEBUG to clean the code.
Signed-off-by: Michal Simek
---
arch/microblaze/lib/bootm.c | 15 +--
1 file changed, 9 insertions(+), 6
There is no need to show FDT message in regular flow that's why switch it
to debug level.
Fixes: 0905046050b0 ("microblaze: Switch to generic bootm implementation")
Signed-off-by: Michal Simek
---
arch/microblaze/lib/bootm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 18/10/2019 22:38, Simon Glass wrote:
Hi Jean-Jacques,
On Tue, 1 Oct 2019 at 05:51, Jean-Jacques Hiblot wrote:
Prepare the way for a managed GPIO API by handling NULL pointers without
crashing nor failing.
VALIDATE_DESC() and validate_desc() come straight from Linux.
Signed-off-by:
Hi Jagan,
Gentle ping.
As discussed half a year ago, please do not trash this series :)
Miquel Raynal wrote on Thu, 3 Oct 2019
19:55:15 +0200:
> Hi Miquel,
>
> Miquel Raynal wrote on Thu, 3 Oct 2019
> 19:50:02 +0200:
>
> > Hello,
> >
> > A year ago, while working on SPI-NAND support in
Hi Daniel,
On 18.10.19 15:13, Daniel Schwierzeck wrote:
The deadline for migration to CONFIG_DM is v2020.01. The VCT
baords would need an almost complete rewrite of all drivers to
support driver model.
Unless someone has access to the hardware and volunteers to do the migration,
the board
From: Tero Kristo
TPS6236x is a family of step down DC-DC converters optimized for battery
powered portable applications for a small solution size. Add a regulator
driver for supporting these devices.
Signed-off-by: Tero Kristo
Signed-off-by: Keerthy
---
drivers/power/regulator/Kconfig
From: Tero Kristo
Enable AVS class 0 support for the R5 SPL bootloader.
Signed-off-by: Tero Kristo
Signed-off-by: Keerthy
---
configs/am65x_evm_r5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index
From: Tero Kristo
Enable wkup_i2c0 as this is needed for voltage control.
Signed-off-by: Tero Kristo
Signed-off-by: Keerthy
---
arch/arm/dts/k3-am654-r5-base-board.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts
Initialize AVS class 0 so that mpu voltage rail is
programmed to the AVS class 0 compensated value.
Signed-off-by: Keerthy
---
Changes in v2:
* Now that AVS is misc device do not go by default ID 0
and rely on uclass_get_device_by_driver to get the right device.
From: Tero Kristo
MPU voltage on AM65x-evm is controlled via the TPS62363 chip attached
to i2c0 bus. Add device node for this so that it can be controlled via
a regulator driver.
Signed-off-by: Tero Kristo
Signed-off-by: Keerthy
---
arch/arm/dts/k3-am654-r5-base-board.dts | 13 +
Add optional parameter to 'avb verify' sub-command, so that user is able
to specify which slot to use, in case when user's partitions are
slotted. If that parameter is omitted, the behavior of 'avb verify' will
be the same as before, so user API is content.
Signed-off-by: Sam Protsenko
> -Original Message-
> From: Simon Glass [mailto:s...@chromium.org]
> Sent: Sunday, October 20, 2019 8:38 PM
> To: U-Boot Mailing List
> Cc: Bin Meng ; Simon Glass ;
> Andy Shevchenko ; Bernhard Messerklinger
> ; Park, Aiden
> ; Simon Goldschmidt
> ; Stefan Roese
> Subject: [PATCH v3
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