Hi Bin
> Hi Rick,
>
> On Thu, May 28, 2020 at 4:24 PM Bin Meng wrote:
> >
> > Hi Rick,
> >
> > On Thu, May 28, 2020 at 4:17 PM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > > Sent: Wednesday, May 20, 2020 3:40 PM
> > > > To: Rick Jian-Zhi
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Wednesday, May 27, 2020 5:05 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Atish Patra; Bin Meng
> Subject: [PATCH 2/2] riscv: sbi: Move sbi_probe_extension() out of
> CONFIG_SBI_V01
>
> From: Bin Meng
>
> sbi_probe_extension()
On 01. 06. 20 8:59, Johannes Krottmayer wrote:
> Okay, thanks for the fast reply!
>
> At the time I wrote this mail, I didn't read the docs.
>
> Off-topic:
>
> Are there plans for U-Boot to create a default image (including
> FSBL, bitstream and U-Boot)?
>
> For example (additional build
Hi Bin
> Hi Rick,
>
> On Thu, May 28, 2020 at 4:17 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > Sent: Wednesday, May 20, 2020 3:40 PM
> > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> > > Cc: Bin Meng
> > > Subject: [PATCH 2/2] riscv:
Hi Rick,
On Mon, Jun 1, 2020 at 5:08 PM Rick Chen wrote:
>
> Hi Bin
>
> > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > Sent: Wednesday, May 27, 2020 5:05 PM
> > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> > > Cc: Atish Patra; Bin Meng
> > > Subject: [PATCH 2/2] riscv: sbi: Move
On Sun, May 31, 2020 at 09:15:15PM -0700, Bin Meng wrote:
> PCI Firmware specification requires _UID() and doesn't require _ADR()
> to be set. Replace latter by former. This fixes the following warning
> reported by ACPICA 20200430:
>
> Warning 3073 - Multiple types (Device object requires
Hi Rick,
On Mon, Jun 1, 2020 at 3:36 PM Rick Chen wrote:
>
> Hi Bin
>
> > Hi Rick,
> >
> > On Thu, May 28, 2020 at 4:17 PM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > > Sent: Wednesday, May 20, 2020 3:40 PM
> > > > To: Rick Jian-Zhi
Hi Rick,
On Mon, Jun 1, 2020 at 4:14 PM Rick Chen wrote:
>
> Hi Bin
>
> > From: Bin Meng [mailto:bmeng...@gmail.com]
> > Sent: Wednesday, May 27, 2020 5:05 PM
> > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> > Cc: Atish Patra; Bin Meng
> > Subject: [PATCH 1/2] riscv: sbi: Remove
Hi Rick,
On Mon, Jun 1, 2020 at 3:40 PM Rick Chen wrote:
>
> Hi Bin
>
> > Hi Rick,
> >
> > On Thu, May 28, 2020 at 4:24 PM Bin Meng wrote:
> > >
> > > Hi Rick,
> > >
> > > On Thu, May 28, 2020 at 4:17 PM Rick Chen wrote:
> > > >
> > > > Hi Bin
> > > >
> > > > > From: Bin Meng
Okay, thanks for the fast reply!
At the time I wrote this mail, I didn't read the docs.
Off-topic:
Are there plans for U-Boot to create a default image (including
FSBL, bitstream and U-Boot)?
For example (additional build step):
$ export BITSTREAM=/path/to/fpga.bit
For now I use Vivado to
Hi Bin
> > From: Bin Meng [mailto:bmeng...@gmail.com]
> > Sent: Wednesday, May 27, 2020 5:05 PM
> > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> > Cc: Atish Patra; Bin Meng
> > Subject: [PATCH 2/2] riscv: sbi: Move sbi_probe_extension() out of
> > CONFIG_SBI_V01
> >
> > From: Bin Meng
> >
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Wednesday, May 27, 2020 5:05 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Atish Patra; Bin Meng
> Subject: [PATCH 1/2] riscv: sbi: Remove sbi_spec_version
>
> From: Bin Meng
>
> U-Boot defaults to use SBI v0.2. Howerver
Update the firmware to improve compatibility for none-intel USB
host controller.
Signed-off-by: Hayes Wang
---
drivers/usb/eth/r8152.h| 8 +
drivers/usb/eth/r8152_fw.c | 481 -
2 files changed, 265 insertions(+), 224 deletions(-)
diff --git
On 2020/6/1 上午12:01, b.l.huang wrote:
The ROCK-PI-E is a credit card size SBC based on Rockchip RK3328
Quad-Core ARM Cortex A53.
Net - Dual ethernet port, 1 X Gbe, 1 X 100M
USB - USB 3.0
DC - USB-Type C, 5V 2A
Storage - TF card, eMMC
Just build idbloader.img and
On 2020/6/1 上午12:02, b.l.huang wrote:
This commit add the default configuration file and relevant description
for rock-pi-e board
Signed-off-by: Banglang Huang
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/rockchip/evb_rk3328/MAINTAINERS | 7 ++
Marek Vasut [mailto:ma...@denx.de]
> Sent: Tuesday, June 02, 2020 12:46 AM
> > Update the firmware to improve compatibility for none-intel USB
> > host controller.
>
> Can you be more specific about the problem you are fixing here ?
> What is the problem ?
There is low probability that the
On Mon, Jun 1, 2020 at 12:15 PM Bin Meng wrote:
>
> PCI Firmware specification requires _UID() and doesn't require _ADR()
> to be set. Replace latter by former. This fixes the following warning
> reported by ACPICA 20200430:
>
> Warning 3073 - Multiple types (Device object requires either a
Hi Tom,
This PR includes the following x86 changes for v2020.07:
- Corrected some FSP-M/FSP-S settings for Chromebook Coral
- ICH SPI driver and mrccache fixes for obtaining the SPI memory map
- Fixed various warnings generated by latest version IASL when
compiling ACPI tables
The following
Hi Kurt,
On 2020/6/2 上午4:30, Kurt Miller wrote:
On at least the RockPro64, many cards will trip a
synchronous abort when first accessing PCIe config space
during bus scanning. A delay after link training allows
some of these cards to function.
Signed-off-by: Kurt Miller
---
On the RockPro64,
Add CA Ethernet support for the Cortina Access
Presidio Engineering Board
Signed-off-by: Alex Nemirovsky
---
arch/arm/dts/ca-presidio-engboard.dts| 7 +++
board/cortina/presidio-asic/presidio.c | 21 +
configs/cortina_presidio-asic-emmc_defconfig | 4
From: Aaron Tseng
Add Cortina Access Ethernet device driver for CA SoCs.
This driver supports both legacy and DM_ETH network models.
Signed-off-by: Aaron Tseng
Signed-off-by: Alex Nemirovsky
CC: Joe Hershberger
CC: Abbie Chang
CC: Tom Rini
---
MAINTAINERS |4 +
On Thu, May 28, 2020 at 08:08:32AM +, Patrick DELAUNAY wrote:
> Hi Tom,
>
> Please pull the STM32 related patches for v2020.07: u-boot-stm32-20200528
>
> With the following changes:
> - stm32mp15: fix DT on DHCOR SOM and avenger96 board
> - stm32mp15: re-enable KS8851 on DHCOM
>
>
> CI
On Mon, Jun 01, 2020 at 05:18:44PM +0200, Matthias Brugger wrote:
> Hi Tom,
>
> Please have a look at the second round of patches for RPi.
> The two patches fixes 8 GB detection on RPi4 and kernel CI booting.
>
> Regards,
> Matthias
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
On Mon, Jun 1, 2020 at 4:42 PM Andy Shevchenko
wrote:
>
> On Sun, May 31, 2020 at 09:15:15PM -0700, Bin Meng wrote:
> > PCI Firmware specification requires _UID() and doesn't require _ADR()
> > to be set. Replace latter by former. This fixes the following warning
> > reported by ACPICA 20200430:
On Mon, Jun 1, 2020 at 12:15 PM Bin Meng wrote:
>
> Create buffers outside of the methods as ACPICA 20200430 complains
> about this:
>
> Remark 2173 - Creation of named objects within a method is highly
> inefficient, use globals or method local variables instead
>
Hi Tom,
Didn't check the update for checkpatch.pl, but my point for code line
length is:
Warning is necessary for 80 characters exceed, so author and reviewer
can notice it, but it's case by case, if this is reasonable, it's OK to
exceed 80
characters for better readability.
Heinrich,
On Fri, May 29, 2020 at 12:37:26PM +0200, Heinrich Schuchardt wrote:
> On 5/29/20 8:41 AM, AKASHI Takahiro wrote:
> > UEFI specification requires that we shall support three type of
> > certificates of authenticode in PE image:
> > WIN_CERT_TYPE_EFI_GUID with the guid,
在 2020/6/2 9:59, Kever Yang 写道:
Hi Kurt,
On 2020/6/2 上午4:30, Kurt Miller wrote:
On at least the RockPro64, many cards will trip a
synchronous abort when first accessing PCIe config space
during bus scanning. A delay after link training allows
some of these cards to function.
Signed-off-by:
Move it out of lowlevel.S into spintable.S. On layerscape, the secondary
CPUs are brought up in main u-boot. This will make it possible to only
compile the spin table code for the main u-boot and omit it in SPL.
This saves about 720 bytes in the SPL.
Signed-off-by: Michael Walle
---
Fix the alignment so it will match the comments. The spin table has to
be 8 byte aligned, so ".align 3" is enough.
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Make the print of the starting address a debug output and pretty print
the info about online cores.
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
Document SPI flash program steps for rockchip platforms.
Suggested-by: Hugh Cole-Baker
Signed-off-by: Jagan Teki
---
doc/board/rockchip/rockchip.rst | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/doc/board/rockchip/rockchip.rst
There are two issues:
(1) The spin table doesn't convert the endianness of the jump address.
Although there is code for it, the result isn't used at all (x0).
(2) If something goes wrong, the function returns. But that doesn't
make sense at all.
Use the actual converted jump address
From: Arthur Li
Add I2C controller support for Cortina Access CA SoCs
Signed-off-by: Arthur Li
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
Reviewed-by: Heiko Schocher
---
Changes in v9:
- specially include bitops.h and delay.h which
were removed from common.h
Changes in v8:
-
Add I2C board support for Cortina Access Presidio Engineering Board
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
Reviewed-by: Heiko Schocher
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v4: None
Add a new variable secondary_boot_code_start, which holds a pointer to
the start of the spin table code. This will help to relocate the code
section. While at it, move the size variable from the end to the
beginning so there is a common section for the variables. Remove any
other symbols.
On at least the RockPro64, many cards will trip a
synchronous abort when first accessing PCIe config space
during bus scanning. A delay after link training allows
some of these cards to function.
Signed-off-by: Kurt Miller
---
On the RockPro64, some pci cards trip a synchronous abort when
> On Jun 1, 2020, at 9:45 AM, Jagan Teki wrote:
>
> On Fri, May 22, 2020 at 6:18 AM Alex Nemirovsky
> wrote:
>>
>> From: Pengpeng Chen
>>
>> Add SPI Flash controller driver for Cortina Access
>> CA SoCs
>>
>> Signed-off-by: Pengpeng Chen
>> Signed-off-by: Alex Nemirovsky
>> CC:
On Fri, 2020-05-29 at 13:00 -0600, Simon Glass wrote:
> Hi Kurt,
>
> On Fri, 29 May 2020 at 06:42, Kurt Miller wrote:
> >
> >
> > On Fri, 2020-05-29 at 09:27 +0100, Peter Robinson wrote:
> > >
> > > On Thu, May 28, 2020 at 8:32 PM Kurt Miller
> > > wrote:
> > > >
> > > >
> > > >
> > > >
On rockchip platforms, SPI boot image creation is not
straightforward like MMC boot image creation where former
requires to specify tpl, spl in multimage format in mkimage,
and later simply do a concatenate mkimaged-tpl with spl.
On this note, let drop rkspi image type creation via kbuild
and let
Mark the default U-Boot environment as SPI flash since
this is an on board flash device.
Signed-off-by: Jagan Teki
---
configs/roc-pc-rk3399_defconfig | 3 ++-
include/configs/roc-pc-rk3399.h | 4
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git
U-Boot TPL 2020.07-rc3-00090-gd4e919f927-dirty (Jun 01 2020 - 23:45:53)
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
256B stride
lpddr4_set_rate:
I have marked this series as v2, since the previous
one has SPL SPI boot via different defconfig.
Thanks to Hugh Cole-Baker for inputs about SPI boot
image creation.
Changes for v2:
- same defconfig to support both MMC, SPI boot
- add spi flash program document
Any inputs?
Jagan.
Jagan Teki
Did I miss the maintainer for this series?
Dan
On 5/11/20 7:52 PM, Dan Murphy wrote:
Bump to the series
On 5/4/20 4:14 PM, Dan Murphy wrote:
Hello
The addition of the DP83867 driver to uboot was done in a generic way
that
made it a bit difficult to bring in new PHY drivers. The difficulty
This function is not used outside the module. Make it static.
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index
The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.
Only the PowerPC architecture needs this function. Remove it.
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape/mp.c| 5 -
arch/arm/include/asm/arch-fsl-layerscape/mp.h | 1 -
2 files changed, 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
Now that the spin table is in a separate module, this is no longer
necessary. Drop it.
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S
On ARM64, a 64kb region is reserved for the runtime services code.
Unfortunately, this code overlaps with the spin table code, which also
needs to be reserved. Thus now that the code is relocatable, allocate a
new page from EFI, copy the spin table code into it, update any pointers
to the old
There is no need to cast around. Assign the address to the local
variable and use it.
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
Fix bootefi on layerscape boards which use spin table for secondary cores
bringup. There two main issues here:
(1) bootefi doesn't kick the secondary cores
(2) bootefi reserves a 64kb region for runtime services code on ARM64
which overlaps the spin table code.
We will fix (1) by removing
Spin tables are broken with bootefi. This is because - in contrast to
the booti call chain - there is no call to smp_kick_all_cpus(). Due to
this missing call the secondary CPUs are never released from their "wait
for interrupt state", see secondary_boot_func() in lowlevel.S.
Originally, this
Don't use LDR to load a pointer to a function. This will generate a
literal which cannot be relocated. Use ADR which is PC-relative and
therefore can easily be relocated.
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 6 +++---
1 file changed, 3 insertions(+),
> On Jun 1, 2020, at 9:48 AM, Jagan Teki wrote:
>
> On Fri, May 22, 2020 at 6:18 AM Alex Nemirovsky
> wrote:
>>
>> Add SPI NOR support for Cortina Access
>> Presidio Engineering Board
>>
>> Signed-off-by: Alex Nemirovsky
>> CC: Jagan Teki
>> CC: Vignesh R
>> CC: Tom Rini
>>
>> ---
>>
On Tue, Jun 2, 2020 at 2:00 AM Kurt Miller wrote:
>
> On at least the RockPro64, many cards will trip a
> synchronous abort when first accessing PCIe config space
> during bus scanning. A delay after link training allows
> some of these cards to function.
Can you check does the SoC has external
Hi Simon,
On 26/5/20 15:39, Walter Lozano wrote:
Hi Simon,
On 25/5/20 18:40, Simon Glass wrote:
Hi Tom,
On Mon, 25 May 2020 at 14:57, Tom Rini wrote:
On Mon, May 25, 2020 at 02:34:20PM -0600, Simon Glass wrote:
Hi Tom,
On Mon, 25 May 2020 at 13:47, Tom Rini wrote:
On Mon, May 25, 2020
Add SPI NOR support for Cortina Access
Presidio Engineering Board
Signed-off-by: Alex Nemirovsky
CC: Jagan Teki
CC: Vignesh R
CC: Tom Rini
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v5:
- NAND support removed from presidio-asic board DT.
Changes in v3: None
From: Pengpeng Chen
Add SPI Flash controller driver for Cortina Access
CA SoCs
Signed-off-by: Pengpeng Chen
Signed-off-by: Alex Nemirovsky
CC: Jagan Teki
CC: Vignesh R
CC: Tom Rini
---
Changes in v9:
- Clean up MAINTAINERS changes
Changes in v8:
- No code change
- Split out
Add Parallel NAND CA support to Cortina Access
Presidio Engineering Board support
Signed-off-by: Alex Nemirovsky
CC: Miquel Raynal
CC: Simon Glass
---
Changes in v2: None
configs/cortina_presidio-asic-bch16_defconfig | 35 ++
Hi Pratyush,
On Fri, 29 May 2020 at 16:04, Pratyush Yadav wrote:
>
> Prepare the way for a managed GPIO API by handling NULL pointers without
> crashing or failing. validate_desc() comes from Linux with the prints
> removed to reduce code size.
Please can you add a little detail as to why this
Hi Pratyush,
On Mon, 1 Jun 2020 at 05:22, Pratyush Yadav wrote:
>
> On 31/05/20 08:08AM, Simon Glass wrote:
> > Hi Pratyush,
> >
> > On Fri, 29 May 2020 at 15:39, Pratyush Yadav wrote:
> > >
> > > Hi,
> > >
> > > This is a re-submission of Jean-Jacques' earlier work in October last
> > > year.
Hi Tom,
Please have a look at the second round of patches for RPi.
The two patches fixes 8 GB detection on RPi4 and kernel CI booting.
Regards,
Matthias
---
The following changes since commit 29b0540d5acc35c8096d7147d7574d0b3ae7dcc0:
Merge tag 'bugfixes-for-v2020.07-rc4' of
Hi again,
On 01/06/2020 17:18, Matthias Brugger wrote:
> Hi Tom,
>
> Please have a look at the second round of patches for RPi.
> The two patches fixes 8 GB detection on RPi4 and kernel CI booting.
>
I forgot to add the links to the CI:
https://travis-ci.org/github/mbgg/u-boot/builds/692983026
On Fri, May 8, 2020 at 4:31 AM Samuel Holland wrote:
>
> When compiling with CONFIG_SPL_SERIAL=n, gcc warns about
> mbus_configure_port not being marked as static:
>
> In file included from include/common.h:34,
> from arch/arm/mach-sunxi/dram_sunxi_dw.c:11:
> include/log.h:185:4:
On Fri, May 8, 2020 at 4:40 AM Samuel Holland wrote:
>
> While the R40 uses a different register for EMAC clock configuration
> than other chips, the register has a very similar layout. Reuse the
> existing bitfield definitions in this file, since they match.
>
> This allows the driver to compile
env_flash is a global flash pointer, and the probe would
happen only if env_flash is NULL, but there is no checking
and free the pointer if is not NULL.
So, this patch frees the old env_flash, and get the probed
flash in to env_flash pointer and finally check if is not NULL.
Suggested-by:
On Wed, May 13, 2020 at 2:22 AM Roman Stratiienko
wrote:
>
> H6 SOC needs additional initialization of PHY registers. Corresponding
> changes can be found in the kernel patch [1].
>
> Without this changes there is no enumeration of 'musb' gadget.
>
> [1] -
>
On Tue, Apr 28, 2020 at 9:26 PM Benedikt-Alexander Mokroß
wrote:
>
> According to the Datasheet, the V3s has a 32KiB SRAM.
> This patch corrects CONFIG_SPL_MAX_SIZE and LOW_LEVEL_SRAM_STACK
> accordingly.
Look like the existing value has taken from allwinner BSP, but did you
find any issues with
On Fri, May 8, 2020 at 4:49 AM Samuel Holland wrote:
>
> Some boards, specifically 64-bit Allwinner boards (sun50i), are
> extremely limited on SPL size. One strategy that was used to make space
> was to remove the FIT "os" property parsing code, because it uses a
> rather large lookup table.
>
>
On Tue, 2020-05-05 at 18:26 +0200, Nicolas Saenz Julienne wrote:
> Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be
> loaded explicitly. Earlier versions didn't need that as they where using
> an EEPROM for that purpose. This series takes care of setting up the
> relevant
On 6/1/20 4:41 PM, Nicolas Saenz Julienne wrote:
> On Mon, 2020-06-01 at 13:12 +0200, Marek Vasut wrote:
>> On 6/1/20 1:09 PM, Nicolas Saenz Julienne wrote:
>>> On Mon, 2020-06-01 at 12:53 +0200, Marek Vasut wrote:
On 6/1/20 12:47 PM, Nicolas Saenz Julienne wrote:
> On Tue, 2020-05-05 at
On 6/1/20 4:43 PM, André Przywara wrote:
> On 01/06/2020 14:56, Heinrich Schuchardt wrote:
>> Provide accurate values of the manufacturer and the product name.
>>
>> PINE Microsystems Inc. is referred to on https://www.pine64.org/contact/.
>
> While this patch looks alright, I wonder if we can
On Fri, May 22, 2020 at 6:18 AM Alex Nemirovsky
wrote:
>
> Add SPI NOR support for Cortina Access
> Presidio Engineering Board
>
> Signed-off-by: Alex Nemirovsky
> CC: Jagan Teki
> CC: Vignesh R
> CC: Tom Rini
>
> ---
>
> Changes in v8: None
> Changes in v7: None
> Changes in v5:
> - NAND
DM_SPI migration status fror v2020.07
removed:
lpc32xx_ssp.c
sh_spi.c
Signed-off-by: Jagan Teki
---
doc/driver-model/migration.rst | 2 --
1 file changed, 2 deletions(-)
diff --git a/doc/driver-model/migration.rst b/doc/driver-model/migration.rst
index d1fc0e6a78..de8c1f9e72 100644
---
On 01/06/2020 14:56, Heinrich Schuchardt wrote:
> Provide accurate values of the manufacturer and the product name.
>
> PINE Microsystems Inc. is referred to on https://www.pine64.org/contact/.
While this patch looks alright, I wonder if we can just use the "model"
property in the DT's root
Hi Tom,
Please take into account this second round of patches for v2020.07.
Basically we fix RPi4 with 8 GB as up to now U-Boot didn't detect all memory
banks. The new RPi4 has 4 memory banks. This leads to the efi stub announcing
the wrong amount of memory to the kernel.
The second patch fixes
On Mon, Jun 01, 2020 at 07:50:17AM +0800, Kever Yang wrote:
> Hi Tom,
>
> Please pull the rockchip updates/fixes:
> - Fix mmc of path after syncfrom kernel dts;
> - Add dwc3 host support with DM for rk3399;
> - Add usb2phy and typec phy for rockchip platform;
> - Migrate board list doc to
On Mon, Jun 1, 2020 at 1:55 PM Roman Kovalivskyi
wrote:
>
> On 27.05.20 15:56, Alex Kiernan wrote:
>
> > On Wed, May 27, 2020 at 12:14 PM Roman Kovalivskyi
> > wrote:
> >> From: Roman Stratiienko
> >>
> >> Android 10 adds support for dynamic partitions and in order to support
> >> them
On Wed, May 27, 2020 at 7:03 PM Benedikt-Alexander Mokroß
wrote:
>
> This optional patch adds the needed device-tree node to sun8i-v3s.dtsi to
> enable
> ethernet for sun8i-v3s boards.
Better to sync the dts(i) from Linux (-next) with proper tag details.
On Fri, May 22, 2020 at 6:18 AM Alex Nemirovsky
wrote:
>
> From: Pengpeng Chen
>
> Add SPI Flash controller driver for Cortina Access
> CA SoCs
>
> Signed-off-by: Pengpeng Chen
> Signed-off-by: Alex Nemirovsky
> CC: Jagan Teki
> CC: Vignesh R
> CC: Tom Rini
>
> ---
>
> Changes in v8:
>
On 6/1/20 10:42 AM, Hayes Wang wrote:
> Update the firmware to improve compatibility for none-intel USB
> host controller.
Can you be more specific about the problem you are fixing here ?
What is the problem ?
On 5/30/20 2:22 AM, Marek Vasut wrote:
> Add Kconfig entry for the PFUZE PMIC, SPL variant.
>
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Jaehoon Chung
> Cc: Peng Fan
> Cc: Stefano Babic
Reviewed-by: Jaehoon Chung
> ---
> drivers/power/pmic/Kconfig | 7 +++
> 1 file
On 31/05/20 08:08AM, Simon Glass wrote:
> Hi Pratyush,
>
> On Fri, 29 May 2020 at 15:39, Pratyush Yadav wrote:
> >
> > Hi,
> >
> > This is a re-submission of Jean-Jacques' earlier work in October last
> > year. It can be found at [0]. The goal is to facilitate porting drivers
> > from the linux
On 27.05.20 15:56, Alex Kiernan wrote:
> On Wed, May 27, 2020 at 12:14 PM Roman Kovalivskyi
> wrote:
>> From: Roman Stratiienko
>>
>> Android 10 adds support for dynamic partitions and in order to support
>> them userspace fastboot must be used[1]. New tool fastbootd is
>> included into
Hey all,
As I see tech sites are noting that Linus has changed the kernel's code
style to no longer be so strict about 80 character line width, I figured
I should say something here given how much we follow the Linux kernel
anyhow.
Given that we've long told people to ignore checkpatch for dts
On 6/1/20 4:30 AM, Peng Fan wrote:
>> Subject: [PATCH v3] spl: allow board_spl_fit_post_load() to fail
>>
>> On i.MX platforms board_spl_fit_post_load() can check the loaded SPL image
>> for authenticity using its HAB engine. U-Boot's SPL mechanism allows
>> booting images from other sources as
On 6/1/20 12:47 PM, Nicolas Saenz Julienne wrote:
> On Tue, 2020-05-05 at 18:26 +0200, Nicolas Saenz Julienne wrote:
>> Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be
>> loaded explicitly. Earlier versions didn't need that as they where using
>> an EEPROM for that purpose.
On Mon, Jun 01, 2020 at 05:23:09AM +, Priyanka Jain wrote:
> >-Original Message-
> >From: Tom Rini
> >Sent: Friday, May 29, 2020 1:32 AM
> >To: Priyanka Jain
> >Cc: Jagan Teki ; Simon Glass
> >; u-boot@lists.denx.de; linux-
> >amar...@amarulasolutions.com
> >Subject: Re: [PATCH
smbios_add_string() cannot deal with empty strings. This leads to incorrect
property values and invalid tables. E.g. for the pine64-lts_defconfig
CONFIG_SMBIOS_MANUFACTURER="". Linux command dmidecode shows:
Table 1:
Manufacturer: sunxi
Product Name: sunxi
Table 3:
Invalid entry
On 31.05.20 17:34, Heinrich Schuchardt wrote:
> On 5/22/20 8:12 PM, Heinrich Schuchardt wrote:
>> On 5/22/20 5:21 PM, Jan Kiszka wrote:
>>> On 22.05.20 16:55, Heinrich Schuchardt wrote:
On 22.05.20 14:21, Jan Kiszka wrote:
> On 22.05.20 13:38, Heinrich Schuchardt wrote:
>> Am May 22,
From: Razvan Becheriu
Add part block sub-command which returns block size.
e.g.:
part block mmc $mmcdev system_a system_a_index
Signed-off-by: Razvan Becheriu
---
cmd/part.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/cmd/part.c b/cmd/part.c
index
The Intel Edison OTA process requires a conversion of data size
from bytes to number of blocks. The following functions are used:
# function ota_conv_sizes
# Convert a bytes size to a block size
# input bytesize : size in bytes to convert
# input blksize : size of a
On Mon, 2020-06-01 at 12:53 +0200, Marek Vasut wrote:
> On 6/1/20 12:47 PM, Nicolas Saenz Julienne wrote:
> > On Tue, 2020-05-05 at 18:26 +0200, Nicolas Saenz Julienne wrote:
> > > Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be
> > > loaded explicitly. Earlier versions
Provide accurate values of the manufacturer and the product name.
PINE Microsystems Inc. is referred to on https://www.pine64.org/contact/.
Signed-off-by: Heinrich Schuchardt
---
configs/pine64-lts_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/pine64-lts_defconfig
On 6/1/20 1:09 PM, Nicolas Saenz Julienne wrote:
> On Mon, 2020-06-01 at 12:53 +0200, Marek Vasut wrote:
>> On 6/1/20 12:47 PM, Nicolas Saenz Julienne wrote:
>>> On Tue, 2020-05-05 at 18:26 +0200, Nicolas Saenz Julienne wrote:
Newer revisions of the RPi4 need their xHCI chip, VL805, firmware
On 01.06.20 at 10:18, Michal Simek wrote:
> SPL is community effort and not supported flow by Xilinx. If you want to
> use it, use it but don't expect any help from Xilinx to help you with
> issues. I take care about it, use it but there is no planning behind. I
> am fixing issues for me and for
On Mon, 2020-06-01 at 13:12 +0200, Marek Vasut wrote:
> On 6/1/20 1:09 PM, Nicolas Saenz Julienne wrote:
> > On Mon, 2020-06-01 at 12:53 +0200, Marek Vasut wrote:
> > > On 6/1/20 12:47 PM, Nicolas Saenz Julienne wrote:
> > > > On Tue, 2020-05-05 at 18:26 +0200, Nicolas Saenz Julienne wrote:
> > >
On Tue, 2020-06-02 at 02:16 +0530, Jagan Teki wrote:
> On Tue, Jun 2, 2020 at 2:00 AM Kurt Miller wrote:
> >
> >
> > On at least the RockPro64, many cards will trip a
> > synchronous abort when first accessing PCIe config space
> > during bus scanning. A delay after link training allows
> >
Add Parallel NAND CA support to Cortina Access
Presidio Engineering Board support
Signed-off-by: Alex Nemirovsky
CC: Miquel Raynal
CC: Simon Glass
---
Changes in v3: None
Changes in v2: None
configs/cortina_presidio-asic-bch16_defconfig | 35 ++
It is possible to specify a device tree node for an USB device. This is
useful if you have a static USB setup and want to use aliases which
point to these nodes, like on the Raspberry Pi.
The nodes are matched against their hub port number, the compatible
strings are not matched for now.
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