Hi,
On Mon, Apr 19, 2021 at 04:35:04PM +0100, Andre Przywara wrote:
> On Sun, 18 Apr 2021 22:16:21 -0500
> Samuel Holland wrote:
>
> (CC:ing Maxime)
>
> Hi,
>
> > Currently, the environment is always stored in eMMC if eMMC is enabled
> > in the config. This means images written to SD and eMMC
From: Chaitanya Sakinam
Read Linux PPFE firmware from flash partition and pass it to Linux through
FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs.
(FDT may increase at max by 64KB)
Signed-off-by: Chaitanya Sakinam
Signed-off-by: Anji J
Signed-off-by: Biwen Li
---
Hi Jagan,
On 4/25/2021 9:42 PM, Jagan Teki wrote:
> On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano wrote:
>>
>> On 4/19/2021 4:13 PM, Jagan Teki wrote:
>>> On Wed, Apr 7, 2021 at 9:01 AM wrote:
From: Takahiro Kuwano
The S25HL-T/S25HS-T family is the Cypress Semper Flash
On Mon, Apr 26, 2021 at 08:08:03AM +0900, Yuichiro Goto wrote:
> Use of strcat() against an uninitialized buffer would lead
> to buffer overflow. This patch fixes it.
Reviewed-by: Andy Shevchenko
> Fixes: 694cd5618c ("IOMUX: Introduce iomux_replace_device()")
> Signed-off-by: Yuichiro Goto
>
gd is not used in this file that's why doesn't make sense to declare it.
Signed-off-by: Michal Simek
---
drivers/spi/zynqmp_gqspi.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 900cb2610c7f..eee8e9df0f7d 100644
---
Hi All,
does anyone know of the USB 3.1 support status in mainline U-Boot? I've
only seen these related patches:
commit d92e866f6008fdd6483735c6fd1ed95c8fdc87b1
Author: Chunfeng Yun
Date: Wed Oct 14 15:08:28 2020 +0800
usb: common: add define of usb_speed_string()
There is only
The following changes since commit e1333435afbf0c6290b1d16bb446b57807f75502:
test/py: Bump py to 1.10.0 for CVE-2020-29651 (2021-04-24 13:31:36 -0400)
are available in the Git repository at:
git://source.denx.de/u-boot-sh.git master
for you to fetch changes up to
On Mon, 2021-04-26 at 20:22 +0800, Bin Meng wrote:
> Hi Stefan,
>
> On Mon, Apr 26, 2021 at 6:21 PM Stefan Roese wrote:
> >
> > Hi All,
> >
> > does anyone know of the USB 3.1 support status in mainline U-Boot? I've
> > only seen these related patches:
> >
> > commit
Hi Stefan,
On Mon, Apr 26, 2021 at 6:21 PM Stefan Roese wrote:
>
> Hi All,
>
> does anyone know of the USB 3.1 support status in mainline U-Boot? I've
> only seen these related patches:
>
> commit d92e866f6008fdd6483735c6fd1ed95c8fdc87b1
> Author: Chunfeng Yun
> Date: Wed Oct 14 15:08:28 2020
On Mon, Apr 26, 2021 at 4:57 PM Andre Przywara wrote:
>
> On Sun, 25 Apr 2021 18:03:05 +0530
> Jagan Teki wrote:
>
> Hi Jagan,
>
> thanks for your input!
>
> > On Sun, Apr 25, 2021 at 3:30 PM Andre Przywara
> > wrote:
> > >
> > > On Fri, 16 Apr 2021 12:08:09 +0100
> > > Andre Przywara wrote:
Add the basic functionality required to support the standard crypt
format.
The files crypt-sha256.c and crypt-sha512.c originate from libxcrypt and
their formatting is therefor retained.
The integration is done via a crypt_compare() function in crypt.c.
```
libxcrypt $ git describe --long
In case a user has to enter a complicated password it is sometimes
desireable to give the user more time than the default timeout.
Enabling this feature will disable the timeout entirely in case the user
presses the key before entering any other character.
Signed-off-by: Steffen Jaeckel
The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF
tree") change driver behavior to while loop which wasn't correct because
the driver was looping over again and again. The reason was that
ofnode_valid() is taking 0 as correct value.
Fix it by changing while loop to
In order to have at least one defconfig that enables all those newly added
values.
Signed-off-by: Steffen Jaeckel
---
configs/bcm963158_ram_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig
index
On 22.04.21 16:23, Pali Rohár wrote:
Trying to clear PIO_START register when it is non-zero (which indicates
that previous PIO transfer has not finished yet) causes an External
Abort with SError 0xbf02.
This bug is currently worked around in TF-A by handling External Aborts
in EL3 and
On Mon, Apr 26, 2021 at 6:19 PM Pratyush Yadav wrote:
>
> On 26/04/21 06:04PM, Jagan Teki wrote:
> > On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano
> > wrote:
> > >
> > > Hi Jagan,
> > >
> > > On 4/25/2021 9:42 PM, Jagan Teki wrote:
> > > > On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano
>
Hi Tom,
please pull this branch, containing the late part of the 2021.07 changes.
This fixes the broken H5 Ethernet and updates the R40 and A64 DT files,
so nothing really critical.
Build-tested for all 156 sunxi boards, and boot tested on a A64, R40, H5
and H616 board. USB, SD card, eMMC,
On 26/04/21 06:04PM, Jagan Teki wrote:
> On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano wrote:
> >
> > Hi Jagan,
> >
> > On 4/25/2021 9:42 PM, Jagan Teki wrote:
> > > On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano
> > > wrote:
> > >>
> > >> On 4/19/2021 4:13 PM, Jagan Teki wrote:
> > >>> On
From: Florin Chiculita
Since the new RevC LX2160A-RDB board has its 10G Aquantia PHYs at
different MDIO bus addresses, we must update both the kernel DTS and
u-boot's DTS (in case of DM_ETH) in case the board is indeed RevC.
Use the newly introduced get_board_rev() function to trigger a fixup
of
From: Florin Chiculita
Add new API for obtaining board revision and trigger the i2c node
fixup with this new API.
Signed-off-by: Florin Chiculita
Signed-off-by: Ioana Ciornei
---
board/freescale/lx2160a/lx2160a.c | 13 ++---
board/freescale/lx2160a/lx2160a.h | 6 +-
2 files
Use the newly fdt_fixup_board_phy_revc() function introduced to updated
both kernel's DTS and u-boot's DTS in case we are running with DM_ETH.
Signed-off-by: Ioana Ciornei
Signed-off-by: Florin Chiculita
---
board/freescale/lx2160a/eth_lx2160ardb.c | 2 +-
board/freescale/lx2160a/lx2160a.c
From: Florin Chiculita
New RevC LX2160A-RDB board doesn't have any 40G PHY and the 10G Aquantia
PHYs have different MDIO bus addresses, thus a different init is
required.
This patch adds support for the non-DM_ETH use of the LX2160ARDB RevC
board.
Signed-off-by: Florin Chiculita
Signed-off-by:
On Mon, 19 Apr 2021 at 17:05, Jaehoon Chung wrote:
> > diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> > index d9ab6a0a83..f038debc6c 100644
> > --- a/drivers/mmc/sdhci.c
> > +++ b/drivers/mmc/sdhci.c
> > @@ -708,6 +708,15 @@ static int sdhci_init(struct mmc *mmc)
> >
> >
On Mon, Apr 26, 2021 at 5:45 PM Andre Przywara wrote:
>
> We hardcode the pinctrl setting for the MMC controllers in boards.c,
> since we need them also in the SPL, where there is no DT yet.
>
> Add the respective setting for the H616 SoC, to enable eMMC on boards
> with this SoC as well.
> Also
On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano wrote:
>
> Hi Jagan,
>
> On 4/25/2021 9:42 PM, Jagan Teki wrote:
> > On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano
> > wrote:
> >>
> >> On 4/19/2021 4:13 PM, Jagan Teki wrote:
> >>> On Wed, Apr 7, 2021 at 9:01 AM wrote:
>
> From:
This patch set adds networking support for the LX2160A-RDB revC board.
The main difference is that the 10G Aquantia PHYs are at different MDIO
bus addresses. To address this, the u-boot's DTS (in case of DM_ETH) and
the kernel's DTS need to undergo a fixup.
This patch set applies cleanly on top
We hardcode the pinctrl setting for the MMC controllers in boards.c,
since we need them also in the SPL, where there is no DT yet.
Add the respective setting for the H616 SoC, to enable eMMC on boards
with this SoC as well.
Also to make diagnosing this problem easier, print a warning if a board
On Sun, Apr 25, 2021 at 10:17 PM Dario Binacchi wrote:
>
> This reverts commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc.
>
> As pointed by [1] and [2], the reverted patch made every DT 'reg'
> property translatable. What the patch was trying to fix was fixed in a
> different way from previously
Use the Error values that may be returned by PCI functions
Added the error macro from linux/include/linux/pci.h
drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared (first use in this
Enable EFI capsule update features to be enabled by default also with all
dfu valid options for ZynqMP.
This feature was tested on Xilinx ZynqMP zcu104 board with defining
dfu_alt_info="mmc 0:1=boot.bin fat 0 1;u-boot.itb fat 0 1"
and
dfu_alt_info="sf 0:0=boot.bin raw 0 0x5;u-boot.itb raw
On Sun, 25 Apr 2021 18:03:05 +0530
Jagan Teki wrote:
Hi Jagan,
thanks for your input!
> On Sun, Apr 25, 2021 at 3:30 PM Andre Przywara wrote:
> >
> > On Fri, 16 Apr 2021 12:08:09 +0100
> > Andre Przywara wrote:
> >
> > Hi,
> >
> > > Commit 2243d19e5618 ("mmc: mmc-uclass: Use dev_seq() to
In order to prevent using the global errno, replace it with a static
version and create a wrapper function which returns the error value.
Signed-off-by: Steffen Jaeckel
---
include/crypt.h | 3 ++-
lib/crypt/alg-sha256.h | 6 --
lib/crypt/alg-sha512.h | 6 --
Hook into the autoboot flow as an alternative to the existing
mechanisms.
Signed-off-by: Steffen Jaeckel
---
common/Kconfig.boot | 23 +---
common/autoboot.c | 85 -
2 files changed, 95 insertions(+), 13 deletions(-)
diff --git
While doing code-review internally this got nitpicked by 2 reviewers, so
I decided to include this here.
Signed-off-by: Steffen Jaeckel
Reviewed-by: Simon Glass
---
common/autoboot.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/common/autoboot.c
This patchset introduces support for crypt-style passwords to unlock
the console in autoboot mode.
The implementation of crypt-sha256 and crypt-sha512 originate from
libxcrypt at https://github.com/besser82/libxcrypt.git
Version v4.4.17
Git commit hash 6b110bc
I didn't re-format those two
i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini
from Engicam.
General features:
- NXP i.MX8M Mini
- Up to 2GB LDDR4
- 8/16GB eMMC
- Gigabit Ethernet
- USB 2.0 Host/OTG
- PCIe Gen2 interface
- I2S
- MIPI DSI to LVDS
- rest of i.MX8M Mini features
i.Core MX8M Mini needs to mount on top
/soc@0
aips1
aips2
aips3
clk
iomuxc
osc_24m
are common node enablements across imx8mm platform for dm-spi,
dm-pre-reloc stages.
Move them into common dtsi, imx8mm-u-boot.dtsi
Cc: Tim Harvey
Cc: Adam Ford
Cc: Peng Fan
Cc: Teresa Remmet
Cc: Igor Opaniuk
Signed-off-by: Jagan Teki
---
Changes
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out
i.Core MX8M Mini is an
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.
Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector
i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
i.Core MX8M Mini needs to mount on top of this
Patch series for Engicam i.Core MX8M Mini SOM and it's associated
carrier board dts(i) support.
patch 1: add imx8mm-u-boot.dtsi
patch 2: Engicam i.Core MX8M Mini SoM dtsi
patch 3-4: EDIMM2.2, C.TOUCH 2.0 Carrier boards
Changes for v3:
- rebase on master
- drop header improvement patch
On 26/04/21 06:25PM, Jagan Teki wrote:
> On Mon, Apr 26, 2021 at 6:19 PM Pratyush Yadav wrote:
> >
> > On 26/04/21 06:04PM, Jagan Teki wrote:
> > > On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano
> > > wrote:
> > > >
> > > > Hi Jagan,
> > > >
> > > > On 4/25/2021 9:42 PM, Jagan Teki wrote:
> >
Use udelay instead of msleep fix the below warning.
drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
declaration of function 'msleep' [-Wimplicit-function-declaration]
Cc: Neil Armstrong
Cc: Kever Yang
Signed-off-by: Anand Moon
---
drivers/pci/pcie_dw_rockchip.c | 8
Drop the unused variable warning below.
drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable
'val' [-Wunused-variable]
161 | u32 val;
| ^~~
Cc: Neil Armstrong
Cc: Kever Yang
Signed-off-by: Anand Moon
---
drivers/pci/pcie_dw_rockchip.c | 2 --
1
This patch makes the necessary adjustments in the defconfig to fully
support the CFI flash on the Octeon EBB7304.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Daniel Schwierzeck
---
configs/octeon_ebb7304_defconfig | 5 +++--
1 file changed, 3 insertions(+), 2
Replace debug trace and printf to log macros:
- debug() replaced by dev_dbg() when device is available, this macro
indicate the device name since commit ceb70bb870ac ("dm: Print device
name in dev_xxx like Linux")
- printf() replaced by log_notice() to allow dispatch to log backends.
Use the generic ethernet phy which already manages the correct binding
for gpio reset, including the assert an deassert delays.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- use generic ethernet phy for stm32 variant, this patch is a REWORK of
previous serie: the device parsing is done
Bind any subnode with name beginning by mdio, mdio0 for example,
and not only the "mdio" as namei of subnode.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- update eth-phy driver to support STM32 binding with a mdio0 subnode (NEW)
drivers/net/eth-phy-uclass.c | 10 --
1 file
The gpio reset and the assert or deassert delay are defined in generic
binding of the ethernet phy in Linux:
Documentation/devicetree/bindings/net/ethernet-phy.yaml
reset-gpios:
maxItems: 1
description:
The GPIO phandle and specifier for the PHY reset signal.
reset-assert-us:
Since the commit commit 6a895d039ba7 ("net: Update eQos driver and FEC
driver to use eth phy interfaces") the field phyaddr of driver private data
struct eqos_priv is no more used in eqos_start() for the phy_connect()
parameter.
Now this variable is only initialized in
It is the V2 version of [1] after Marek remarks: all commit are new.
I change the DWC_ETH_QOS STM32 variant by using generic eth phy driver.
This driver is updated to use the gpio reset and assert/deassert delay
from DT with the generic binding defined in linux:
Dne ponedeljek, 26. april 2021 ob 14:14:46 CEST je Andre Przywara napisal(a):
> We hardcode the pinctrl setting for the MMC controllers in boards.c,
> since we need them also in the SPL, where there is no DT yet.
>
> Add the respective setting for the H616 SoC, to enable eMMC on boards
> with
On 4/23/21 11:56 PM, Simon Glass wrote:
Hi Tom, Alex,
On Fri, 23 Apr 2021 at 12:47, Tom Rini wrote:
On Fri, Apr 23, 2021 at 11:55:57AM +1200, Simon Glass wrote:
Hi Alex,
On Thu, 22 Apr 2021 at 07:30, Alex G. wrote:
On 4/21/21 2:15 AM, Simon Glass wrote:
Hi Alexandru,
On Fri, 16 Apr
On Mon, Apr 26, 2021 at 11:50:58AM +0100, Andre Przywara wrote:
>
> Hi Tom,
>
> please pull this branch, containing the late part of the 2021.07 changes.
>
> This fixes the broken H5 Ethernet and updates the R40 and A64 DT files,
> so nothing really critical.
>
> Build-tested for all 156
Define LOG_CATEGORY to allow filtering with log command.
Signed-off-by: Patrick Delaunay
---
drivers/net/dwc_eth_qos.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index e8242ca4e1..e423c31753 100644
--- a/drivers/net/dwc_eth_qos.c
Define LOG_CATEGORY to allow filtering with log command.
Signed-off-by: Patrick Delaunay
---
drivers/net/eth-phy-uclass.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c
index 07aebd935e..abb658bf21 100644
---
Define LOG_CATEGORY to allow filtering with log command.
Signed-off-by: Patrick Delaunay
---
net/eth-uclass.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 34ca731d1e..63ad0908d9 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -5,6 +5,8
It is the V2 version of [1] after Marek remarks: all commit are new.
I change the DWC_ETH_QOS STM32 variant by using generic eth phy driver.
This driver is updated to use the gpio reset and assert/deassert delay
from DT with the generic binding defined in linux:
Add a common empty ops: eqos_null_ops() to remove the duplicated empty
functions and reduce the driver size for stm32 and imx config.
This patch also aligns the prototype of ops 'eqos_stop_clks' with other
eqos ops by adding return value.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
-
At present each invocation of run_steps() updates OUTPUT_FILES_COMMON,
since it does not make a copy of the dict. This is fine for a single
invocation, but for tests, run_steps() is invoked many times.
As a result it may include unwanted items from the previous run, if it
happens that a test runs
Am Mon, Apr 26, 2021 at 01:26:30PM + schrieb Anand Moon:
> Use the Error values that may be returned by PCI functions
> Added the error macro from linux/include/linux/pci.h
>
> drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
> drivers/pci/pcie_dw_rockchip.c:70:10: error:
On 14/04/2021 09.18, Rasmus Villemoes wrote:
> This is a resend of v3 from a year ago. Please consider applying.
>
> v4: rebase to current master.
>
> v3: add fixup patch for mpc83xx_timer, add documentation hunk to
> README, also update m68k instead of only ppc.
>
> v2: add documentation
On Mon, Apr 26, 2021 at 10:21:30PM +0200, Rasmus Villemoes wrote:
> On 14/04/2021 09.18, Rasmus Villemoes wrote:
> > This is a resend of v3 from a year ago. Please consider applying.
> >
> > v4: rebase to current master.
> >
> > v3: add fixup patch for mpc83xx_timer, add documentation hunk to
>
Am Mon, Apr 26, 2021 at 01:26:32PM + schrieb Anand Moon:
> Use udelay instead of msleep fix the below warning.
You sure that's correct? the m in msleep means milli, while the u
in udelay means micro. That's a factor of 1000 of a difference.
> drivers/pci/pcie_dw_rockchip.c:254:3: warning:
Dear Tianrui,
On 4/26/21 12:31 PM, Tianrui Wei wrote:
> This patch adds mmc support for OpenPiton.
> Specifically, some dts bindings were not used because
> our mmc controller doens't have those configuration
> options, it only exposes a dummy mmap interface for
> CPU.
Befere sending patch, how
From: Pratyush Yadav
On devices with non-uniform sector sizes like Spansion S25 or S28 family
of flashes the sector under erase does not necessarily have to be
mtd->erasesize bytes long. For example, on S28 flashes the first 128 KiB
region is composed of 32 4 KiB sectors, then a 128 KiB sector,
From: Takahiro Kuwano
Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or
bottom, depending on the device configuration, while U-Boot supports
uniform sector layout only.
The spansion_erase_non_uniform() erases overlaid 4KB sectors,
non-overlaid portion of normal sector, and
From: Takahiro Kuwano
Some of Spansion/Cypress chips support Read/Write Any Register commands.
These commands are mainly used to write volatile registers and access to
the registers in second and subsequent die for multi-die package parts.
The Read Any Register instruction (65h) is followed by
From: Takahiro Kuwano
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die)
https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links
From: Takahiro Kuwano
Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad
From: Takahiro Kuwano
This patch adds Cypress manufacturer ID (34h) definition.
Signed-off-by: Takahiro Kuwano
Reviewed-by: Pratyush Yadav
---
include/linux/mtd/spi-nor.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index
From: Takahiro Kuwano
For dual/quad die package devices from Spansion/Cypress, the device's
status needs to be checked by reading status registers in all dies, by
using Read Any Register command. To support this, a Flash specific hook
that can overwrite the legacy status check is needed.
From: Takahiro Kuwano
The nor->ready() and spansion_sr_ready() introduced earlier in this
series are used for multi-die package parts.
The nor->quad_enable() sets the volatile QE bit on each die.
The nor->erase() is hooked if the device is not configured to uniform
sectors, assuming it has 32
From: Takahiro Kuwano
The spansion_sr_ready() reads status register 1 by Read Any Register
commnad. This function is called from Flash specific hook with die address
and dummy cycles to support multi-die package parts from Spansion/Cypress.
Signed-off-by: Takahiro Kuwano
Reviewed-by: Pratyush
From: Takahiro Kuwano
Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode.
Cypress chips support B8h to disable 4-byte addressing mode instead of
SPINOR_OP_EX4B(E9h).
This patch defines new opcode and updates set_4byte() to support
enable/disable 4-byte addressing mode
From: Takahiro Kuwano
Fixes mode clocks for SPINOR_OP_READ_FAST_4B in tiny.
Signed-off-by: Takahiro Kuwano
---
Changes in v7:
- No change
Changes in v6:
- Remove spansion_quad_enable_volatile() per comment in
From: Pratyush Yadav
nor->setup() can be used by flashes to configure settings in case they
have any peculiarities that can't be easily expressed by the generic
spi-nor framework. This includes things like different opcodes, dummy
cycles, page size, uniform/non-uniform sector sizes, etc.
Move
From: Pratyush Yadav
Sometimes the information in a flash's SFDP tables is wrong. Sometimes
some information just can't be expressed in the SFDP table. So,
introduce the fixup hooks to allow tailoring settings for a specific
flash.
Three hooks are added: default_init, post_sfdp, and post_bfpt.
From: Pratyush Yadav
These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
Taken from Pratyush's
From: Takahiro Kuwano
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
The summary datasheets can be found in the following links.
https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die)
https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad
On 4/26/21 2:17 PM, Ley Foon Tan wrote:
> Add FIFO mode support for SoCFPGA dwmmc, read "fifo-mode" property from DT.
>
> Signed-off-by: Ley Foon Tan
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/socfpga_dw_mmc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
>
On 4/26/21 12:35 PM, Ley Foon Tan wrote:
> The data read is not working when using FIFO mode.
>
>>From DesignWare databook, when a Data_Transfer_Over (DTO) interrupt is
> received, the software should read the remaining data from FIFO.
>
> Add DTO interrupt checking on data read path and clear
On 4/27/21 2:03 AM, Andre Przywara wrote:
As the comment in musb_regs.h describes, Allwinner saves the
MUSB_CONFIGDATA register, which always return 0 on those SoCs.
This is also true for the H6 and H616, so extend the quirk to those
controllers as well.
This fixes USB peripheral mode on H6
Hey all,
It's release day, and here's v2021.07-rc1. There's a few things I hope
to see a PR for still, and I've talked with Marek about the LTO series
off-list (and I want to get that in for this release still). That said,
as always, I leave what comes in at this point to the discretion of the
On Mon, Apr 26, 2021 at 01:49:15PM +0200, Marek Vasut wrote:
> The following changes since commit e1333435afbf0c6290b1d16bb446b57807f75502:
>
> test/py: Bump py to 1.10.0 for CVE-2020-29651 (2021-04-24 13:31:36 -0400)
>
> are available in the Git repository at:
>
>
On Fri, Apr 23, 2021 at 8:21 AM Marek Vasut wrote:
>
> On 4/23/21 5:04 PM, Tim Harvey wrote:
> > On Thu, Apr 22, 2021 at 12:16 PM Marek Vasut wrote:
> >>
> >> On 4/20/21 2:33 AM, Tim Harvey wrote:
> >>
> >> [...]
> >>
> +/* USB Configs */
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
>
On 4/27/21 2:01 AM, Tim Harvey wrote:
[...]
Why would the power domain get probed/enabled for the usbotg2
bus but not the usbotg1 bus? Here is some debugging:
u-boot=> usb start
starting USB...
Bus usb@32e4: ehci_usb_phy_mode usb@32e4
usb@32e4 probe ret=-22
probe failed, error -22
On 4/26/2021 10:19 PM, Pratyush Yadav wrote:
> On 26/04/21 06:25PM, Jagan Teki wrote:
>> On Mon, Apr 26, 2021 at 6:19 PM Pratyush Yadav wrote:
>>>
>>> On 26/04/21 06:04PM, Jagan Teki wrote:
On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano
wrote:
>
> Hi Jagan,
>
> On
As the comment in musb_regs.h describes, Allwinner saves the
MUSB_CONFIGDATA register, which always return 0 on those SoCs.
This is also true for the H6 and H616, so extend the quirk to those
controllers as well.
This fixes USB peripheral mode on H6 and H616 boards.
Signed-off-by: Andre
Hi Patrick,
On Tue, 27 Apr 2021 at 01:40, Patrick Wildt wrote:
>
> Am Mon, Apr 26, 2021 at 01:26:30PM + schrieb Anand Moon:
> > Use the Error values that may be returned by PCI functions
> > Added the error macro from linux/include/linux/pci.h
> >
> > drivers/pci/pcie_dw_rockchip.c: In
hi Patrick,
On Tue, 27 Apr 2021 at 01:38, Patrick Wildt wrote:
>
> Am Mon, Apr 26, 2021 at 01:26:32PM + schrieb Anand Moon:
> > Use udelay instead of msleep fix the below warning.
>
> You sure that's correct? the m in msleep means milli, while the u
> in udelay means micro. That's a factor
Hi Michal,
On Mon, Apr 26, 2021 at 8:31 PM Michal Simek wrote:
>
> The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF
> tree") change driver behavior to while loop which wasn't correct because
> the driver was looping over again and again. The reason was that
> ofnode_valid()
Hi Tim,
On 26.03.21 16:55, Tim Harvey wrote:
On Thu, Mar 25, 2021 at 11:48 PM Stefan Roese wrote:
On 26.03.21 01:07, Tim Harvey wrote:
The fdt node offset is apparently not set properly when probed
causing no MDIO busses to be found. Fix this by obtaining the
offset.
Signed-off-by: Tim
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