[U-Boot] [PATCH] nds32: Change of NDS32 Custodian

2013-08-03 Thread Andes
Signed-off-by: Andes ub...@andestech.com Cc: Macpaul Lin macp...@gmail.com Cc: Kuan-Yu Kuo ken.ku...@gmail.com --- MAINTAINERS |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 081cf96..c6fd555 100644 --- a/MAINTAINERS +++ b/MAINTAINERS

[U-Boot] [PATCH] nds32: add support for leopard and orca board boot flow auto detect

2014-01-24 Thread Andes
From: rick r...@andestech.com hardware difference between leopard and orca as below: flash setting leoaprd orca bank size 32MB64MB bus width 32-bits 16-bits Signed-off-by: rick r...@andestech.com --- arch/nds32/cpu/n1213/ag101/asm-offsets.c |1 +

[U-Boot] [PATCH] nds32: fix code/data will be corrupted on ram in rum time

2014-02-06 Thread Andes
From: rick r...@andestech.com can not execute get_ram_size(), because the text/data will be corrupted by itself in specific case. Signed-off-by: rick r...@andestech.com Cc: Andes ub...@andestech.com --- board/AndesTech/adp-ag101p/adp-ag101p.c | 18 +++--- 1 files changed, 7

[U-Boot] [PATCH] nds32: Fix compile error.

2016-01-18 Thread Andes
From: rick <r...@andestech.com> Fix compile error with gcc 4.9.3 Signed-off-by: rick <r...@andestech.com> Cc: Andes <ub...@andestech.com> --- arch/nds32/cpu/n1213/start.S |2 +- arch/nds32/include/asm/macro.h | 22 +++--- arch/nds32/include

[U-Boot] [PATCH] nds32: fix mmc rescan hang problem.

2016-01-24 Thread Andes
From: rick When execute mmc rescan command, system will hang. Signed-off-by: rick --- common/cmd_mmc.c |9 + common/env_common.c |3 +++ include/environment.h |3 +++ 3 files changed, 15 insertions(+) diff --git

[U-Boot] [PATCH] nds32: Support relocation.

2016-09-29 Thread Andes
From: rick <r...@andestech.com> Enable pie option for relocation. Signed-off-by: rick <r...@andestech.com> Cc: Andes <ub...@andestech.com> --- arch/nds32/config.mk |2 +- arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 13 +-- arch/nds32

[U-Boot] [PATCH 1/3] nds32: mmc: Support mmc DM.

2016-12-01 Thread Andes
From: rick <r...@andestech.com> Add Andestech mmc DM driver for ag101p board. Do not use get_timer() to check mmc state can improve throughput performance. Signed-off-by: rick <r...@andestech.com> Cc: Andes <ub...@andestech.com> --- drivers/mmc/Kconfig|7 +++ dr

[U-Boot] [PATCH 2/3] nds32: mmc: Support mmc DM.

2016-12-01 Thread Andes
From: rick <r...@andestech.com> Enable mmc DM flow as default for ag101p board. Signed-off-by: rick <r...@andestech.com> c: Andes <ub...@andestech.com> --- board/AndesTech/adp-ag101p/adp-ag101p.c |2 ++ configs/adp-ag101p_defconfig|4 2 files cha

[U-Boot] [PATCH 3/3] nds32: mmc: Support mmc DM.

2016-12-01 Thread Andes
From: rick <r...@andestech.com> Add dts mmc node for ag101p board. Signed-off-by: rick <r...@andestech.com> Cc: Andes <ub...@andestech.com> --- arch/nds32/dts/ag101p.dts |8 1 file changed, 8 insertions(+) diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dt

[U-Boot] [PATCH] nds32: Support serial DM.

2016-11-30 Thread Andes
From: rick <r...@andestech.com> Add device tree source file and enable DM and DM_SERIAL ag101p board can run ns16550 serial DM flow. Signed-off-by: rick <r...@andestech.com> Cc: Andes <ub...@andestech.com> --- arch/Kconfig|1 + arch/nds32/cpu/n1213

[U-Boot] [PATCH] nds32: Support timer DM.

2016-11-30 Thread Andes
From: rick <r...@andestech.com> Add ag101p baord timer DM driver. Signed-off-by: rick <r...@andestech.com> Cc: Andes <ub...@andestech.com> --- arch/nds32/cpu/n1213/ag101/timer.c |3 +- arch/nds32/dts/ag101p.dts |1 + configs/adp-ag101p_defconfig |

[U-Boot] [PATCH] nds32: Support eth DM.

2016-11-30 Thread Andes
From: rick <r...@andestech.com> Add eth DM driver for ag101p board. Enable random ethaddr. Signed-off-by: rick <r...@andestech.com> Cc: Andes <ub...@andestech.com> --- arch/nds32/dts/ag101p.dts |1 + board/AndesTech/adp-ag101p/adp-ag101p.c |

[U-Boot] [PATCH] nds32: Support mmc DM.

2016-11-30 Thread Andes
From: rick <r...@andestech.com> Add Andestech mmc DM driver for ag101p board. Do not use get_timer() to check mmc state can improve throughput performance. Signed-off-by: rick <r...@andestech.com> Cc: Andes <ub...@andestech.com> --- arch/nds32/dts/ag101p.dts

[U-Boot] [PATCH 3/3] nds32: Support AE3XX platform.

2017-05-19 Thread Andes
@@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar <prafu...@marvell.com> +# +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation <nobuh...@andestech.com> +# Macpaul Lin, Andes Technology Corporation &l

[U-Boot] [PATCH 2/3] nds32: Support AG101P timer DM.

2017-05-19 Thread Andes
From: rick Support AG101P timer device tree flow. Signed-off-by: rick --- arch/nds32/cpu/n1213/ag101/timer.c |3 +- arch/nds32/dts/ag101p.dts |8 +++ configs/adp-ag101p_defconfig |2 + drivers/timer/Kconfig |6

[U-Boot] [PATCH 1/3] nds32: Support AG101P serial DM.

2017-05-19 Thread Andes
From: rick Support AG101P serial device tree flow. Signed-off-by: rick --- arch/Kconfig|1 + arch/nds32/cpu/n1213/start.S| 10 +--- arch/nds32/dts/Makefile | 14 +++ arch/nds32/dts/ag101p.dts |

[U-Boot] [PATCH] nds32: eth: Support ftmac100 DM.

2017-05-23 Thread Andes
From: rick Support Andestech eth ftmac100 device tree flow on AG101P/AE3XX platform. Verification: Boot linux kernel via dhcp and bootm ok. NDS32 # setenv bootm_size 0x200;setenv fdt_high 0x1f0; NDS32 # dhcp 0x60 10.0.4.97:boomimage-310y-ae300-spi.bin BOOTP

[U-Boot] [PATCH] nds32: mmc: Support ftsdc010 DM.

2017-05-23 Thread Andes
chip->cfg.f_min = chip->sclk / 0x100; @@ -373,3 +452,4 @@ int ftsdc010_mmc_init(int devid) return 0; } +#endif diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h new file mode 100644 index 000..f74015e --- /dev/null +++ b/drivers/mmc/ftsdc010_mci.h @@

[U-Boot] [PATCH 3/3] nds32: board: Support ftsdc010 DM.

2017-05-30 Thread Andes
From: rick Support Andestech ftsdc010 SD/MMC device tree flow on AG101P/AE3XX platforms. Signed-off-by: rick --- board/AndesTech/adp-ae3xx/adp-ae3xx.c |4 +--- board/AndesTech/adp-ag101p/adp-ag101p.c |7 +-- configs/adp-ae3xx_defconfig

[U-Boot] [PATCH 2/3] nds32: dts: Support ftsdc010 DM.

2017-05-30 Thread Andes
From: rick Support Andestech ftsdc010 SD/MMC device tree flow on AG101P/AE3XX platforms. Signed-off-by: rick --- arch/nds32/dts/ae3xx.dts |8 arch/nds32/dts/ag101p.dts |8 2 files changed, 16 insertions(+) diff --git

[U-Boot] [PATCH 1/3] nds32: mmc: Support ftsdc010 DM.

2017-05-30 Thread Andes
MC_VDD_32_33 | MMC_VDD_33_34; chip->cfg.f_max = chip->sclk / 2; chip->cfg.f_min = chip->sclk / 0x100; @@ -373,3 +452,4 @@ int ftsdc010_mmc_init(int devid) return 0; } +#endif diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h new file

[U-Boot] [PATCH 2/4] nds32: ftsdc010: Support ftsdc010 DM.

2017-06-01 Thread Andes
it a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h new file mode 100644 index 000..63e85ee --- /dev/null +++ b/drivers/mmc/ftsdc010_mci.h @@ -0,0 +1,53 @@ +/* + * Faraday FTSDC010 Secure Digital Memory Card Host Controller + * + * Copyright (C) 2011 Andes Technology Corporation + * Ma

[U-Boot] [PATCH 1/4] nds32: mmc: Support ftsdc010 DM.

2017-06-01 Thread Andes
From: rick Add nds32_mmc to support ftsdc010 dm flow. Signed-off-by: rick --- drivers/mmc/Kconfig | 12 + drivers/mmc/Makefile|1 + drivers/mmc/nds32_mmc.c | 136 +++ 3 files changed, 149

[U-Boot] [PATCH 3/4] nds32: dts: Support ftsdc010 DM.

2017-06-01 Thread Andes
From: rick Add dts to support ftsdc010 dm flow on AG101P/AE3XX platform. Signed-off-by: rick --- arch/nds32/dts/ae3xx.dts |8 arch/nds32/dts/ag101p.dts |8 2 files changed, 16 insertions(+) diff --git

[U-Boot] [PATCH 4/4] nds32: board: Support ftsdc010 DM.

2017-06-01 Thread Andes
From: rick AG101P/AE3XX enable ftsdc010 dm flow. Signed-off-by: rick --- board/AndesTech/adp-ag101p/adp-ag101p.c |2 ++ configs/adp-ae3xx_defconfig |3 +++ configs/adp-ag101p_defconfig|3 +++

[U-Boot] [PATCH] nds32: board: Fix andestech adp-ae3xx.c make fail problem.

2017-09-11 Thread Andes
From: rick Add #include to fix it. Signed-off-by: rick --- board/AndesTech/adp-ae3xx/adp-ae3xx.c |1 + 1 file changed, 1 insertion(+) diff --git a/board/AndesTech/adp-ae3xx/adp-ae3xx.c b/board/AndesTech/adp-ae3xx/adp-ae3xx.c index

[U-Boot] [PATCH] nds32: bootm: Fix warning of struct tag_serialnr declared

2017-09-11 Thread Andes
From: rick move #include from bootm.c to bootm.h Signed-off-by: rick --- arch/nds32/include/asm/bootm.h |2 ++ arch/nds32/lib/bootm.c |1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/nds32/include/asm/bootm.h

[U-Boot] [PATCH] nds32: Fix io.h warning message about readb

2017-09-20 Thread Andes
From: rick It is caused from asm/io.h declare different input type. Signed-off-by: rick --- arch/nds32/include/asm/io.h | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/nds32/include/asm/io.h

[U-Boot] [PATCH 1/3] nds32: mtd: add spi flash id MX25U16335E.

2017-09-13 Thread Andes
From: rick To support MACRONIX MX25U1635E 16M-BIT flash. Signed-off-by: rick --- drivers/mtd/spi/spi_flash_ids.c |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index

[U-Boot] [PATCH 3/3] nds32: spi: Support spi dm driver.

2017-09-13 Thread Andes
G_PIC32_SPI) += pic32_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o diff --git a/drivers/spi/nds_ae3xx_spi.c b/drivers/spi/nds_ae3xx_spi.c new file mode 100644 index 000..f5bd99a --- /dev/null +++ b/drivers/spi/nds_ae3xx_spi.c @@ -0,0 +1,499 @@ +/* + * NDS SPI controller driver. + * + * Copy

[U-Boot] [PATCH 2/3] nds32: board: Support SPI driver.

2017-09-13 Thread Andes
From: rick Add spi dts node and enable spi dm flash config. Signed-off-by: rick --- arch/nds32/dts/ae3xx.dts| 23 +++ configs/adp-ae3xx_defconfig | 10 +- include/configs/adp-ae3xx.h | 15 +-- 3 files

[U-Boot] [PATCH 3/3] nds32: ftmac100: Fix write mac addr fail problem.

2017-09-12 Thread Andes
From: rick After soft reset complete, write mac address immediately will fail. Add delay to work around this problem. Signed-off-by: rick --- drivers/net/ftmac100.c |7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git

[U-Boot] [PATCH 1/3] nds32: ftmac100: support cache enable.

2017-09-12 Thread Andes
From: rick Add cache inval and flush when rx and tx. Signed-off-by: rick --- drivers/net/ftmac100.c |5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index f231e6b..4e45f00 100644

[U-Boot] [PATCH 2/3] nds32: ftmac100 support cache enable.

2017-09-12 Thread Andes
From: rick Enable cache and ftmac100 performance can be improved. Signed-off-by: rick --- arch/nds32/cpu/n1213/start.S | 29 - arch/nds32/include/asm/io.h | 21 + include/configs/adp-ae3xx.h |3

[U-Boot] [PATCH] ae3xx: timer: Fix ae3xx timer work abnormal in 64 bit.

2017-11-14 Thread Andes
From: Rick Chen It will be work fine with unsigned long declaretion in timer register struct when system is 32 bit. But it will not work well when system is 64 bit. Replace it by u32 and verify both ok in 32/64 bit. Signed-off-by: Rick Chen ---

[U-Boot] [PATCH 1/3] ae3xx: timer: Rename AE3XX to ATCPIT100

2017-11-14 Thread Andes
From: Rick Chen ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: Rick Chen --- drivers/timer/Kconfig |7 ++- drivers/timer/Makefile |

[U-Boot] [PATCH] enable debug uart

2017-11-14 Thread Andes
From: rick --- common/board_f.c|2 ++ configs/adp-ae3xx_defconfig |5 + drivers/serial/Kconfig |8 drivers/serial/ns16550.c|5 +++-- include/debug_uart.h|2 ++ lib/display_options.c |2 ++ 6 files

[U-Boot] [PATCH 2/3] nds32: defconfig: Rename AE3XX_TIMER to ATCPIT100_TIMER

2017-11-14 Thread Andes
From: Rick Chen Change AE3XX to its IP name ATCPIT100. Signed-off-by: Rick Chen --- configs/adp-ae3xx_defconfig |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig index

[U-Boot] [PATCH 0/3] ae3xx: timer: Rename AE3XX timer to ATCPIT100

2017-11-14 Thread Andes
From: Rick Chen AE3XX is board name. ATCPIT100 is timer IP name. So rename AE3XX timer to ATCPIT100 timer. Rick Chen (3): ae3xx: timer: Rename AE3XX to ATCPIT100 nds32: defconfig: Rename AE3XX_TIMER to ATCPIT100_TIMER dt-bindings: timer: Add andestech atcpit100 timer

[U-Boot] [PATCH 3/3] dt-bindings: timer: Add andestech atcpit100 timer binding doc

2017-11-14 Thread Andes
.txt @@ -0,0 +1,31 @@ +Andestech ATCPIT100 timer +-- +ATCPIT100 is a generic IP block from Andes Technology, embedded in +Andestech AE3XX, AE250 platforms and other designs. + +This timer is a set of compact multi-function timers, which

[U-Boot] [PATCH 0/3] spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi

2017-11-15 Thread Andes
From: Rick Chen ATCSPI200 is Andestech SPI IP which is embedded in AE3XX and AE250 platforms.So rename it as atcspi200 will be more reasonable to be used in different platforms in the future. Rick Chen (3): spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi nds32:

[U-Boot] [PATCH 1/3] spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi

2017-11-15 Thread Andes
atcspi200_spi.c new file mode 100644 index 000..3e29df0 --- /dev/null +++ b/drivers/spi/atcspi200_spi.c @@ -0,0 +1,499 @@ +/* + * Andestech ATCSPI200 SPI controller driver. + * + * Copyright 2017 Andes Technology, Inc. + * Author: Rick Chen (r...@andestech.com) + * + * SPDX-License-Identifie

[U-Boot] [PATCH 3/3] dt-bindings: spi: Add andestech atcspi200 spi binding doc

2017-11-15 Thread Andes
From: Rick Chen Add a document to describe Andestech atcspi200 spi and binding information. Signed-off-by: Rick Chen --- doc/device-tree-bindings/spi/spi-atcspi200.txt | 37 1 file changed, 37 insertions(+) create mode 100644

[U-Boot] [PATCH 2/3] nds32: defconfig: Rename NDS_AE3XX as ATCSPI200

2017-11-15 Thread Andes
From: Rick Chen Modify Andestech ae3xx board defconfig NDS_AE3XX as ATCSPI200 for spi driver renaming. Signed-off-by: Rick Chen --- configs/adp-ae3xx_defconfig |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[U-Boot] [PATCH] atcpit100: timer: Remove arch dependency.

2017-11-14 Thread Andes
From: Rick Chen ATCPIT100 is often used in AE3XX platform which is based on NDS32 architecture recently. But in the future Andestech will have AE250 platform which is embeded ATCPIT100 timer based on RISCV architecture. Signed-off-by: Rick Chen ---

[U-Boot] [PATCH v3 2/4] cosmetic: atcpit100_timer: Rename function name as atcpit100

2017-11-27 Thread Andes
From: Rick Chen Integrate function and struct name as atcpit100 will be more reasonable. Signed-off-by: rick Signed-off-by: Rick Chen --- drivers/timer/atcpit100_timer.c | 34 +- 1 file changed,

[U-Boot] [PATCH v3 3/4] cosmetic: atcpit100_timer: Use device api to get platdata

2017-11-27 Thread Andes
From: Rick Chen Use dev_get_platdata to get private platdata. Signed-off-by: rick Signed-off-by: Rick Chen --- drivers/timer/atcpit100_timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[U-Boot] [PATCH v3 4/4] dt-bindings: timer: Add andestech atcpit100 timer

2017-11-27 Thread Andes
ode 100644 index 000..620814e --- /dev/null +++ b/doc/device-tree-bindings/timer/atcpit100_timer.txt @@ -0,0 +1,31 @@ +Andestech ATCPIT100 timer +-- +ATCPIT100 is a generic IP block from Andes Technology, embedded in +Andestec

[U-Boot] [PATCH v3 1/4] ae3xx: timer: Rename AE3XX to ATCPIT100

2017-11-27 Thread Andes
From: Rick Chen ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick Signed-off-by: Rick Chen Reviewed-by: Simon Glass

[U-Boot] [PATCH v2 1/3] ae3xx: timer: Rename AE3XX to ATCPIT100

2017-11-26 Thread Andes
From: Rick Chen ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: Rick Chen --- Changelog v2 - Patch 1/3: Changed. - Patch 2/3: Changed. - Patch 3/3: No

[U-Boot] [PATCH v2 2/3] cosmetic: atcpit100_timer: Rename function name as atcpit100

2017-11-26 Thread Andes
From: Rick Chen Integrate function and struct name as atcpit100 will be more reasonable. Signed-off-by: Rick Chen --- drivers/timer/atcpit100_timer.c | 34 +- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git

[U-Boot] [PATCH v2 3/3] dt-bindings: timer: Add andestech atcpit100 timer

2017-11-26 Thread Andes
b/doc/device-tree-bindings/timer/atcpit100_timer.txt @@ -0,0 +1,31 @@ +Andestech ATCPIT100 timer +-- +ATCPIT100 is a generic IP block from Andes Technology, embedded in +Andestech AE3XX, AE250 platforms and other designs. + +This timer i

[U-Boot] [PATCH v2 0/3] Rename ae3xx timer to atcpit100

2017-11-26 Thread Andes
From: Rick Chen Changelog v2 - Patch 1/3: Changed. - Patch 2/3: Changed. - Patch 3/3: No change. Patch 1/3 1. Only rename ae3xx as atcpit100. 2. Squashed Kconfig rename ae3xx into this patch to keep things in a consistent state. Patch 2/3 1. Modify function name

[U-Boot] [PATCH v2 1/3] ae3xx: timer: Rename AE3XX to ATCPIT100

2017-11-26 Thread Andes
From: Rick Chen ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: Rick Chen --- configs/adp-ae3xx_defconfig| 2 +-

[U-Boot] [PATCH v2 0/3] Rename ae3xx timer to atcpit100

2017-11-26 Thread Andes
From: Rick Chen Changelog v2 - Patch 1/3: Changed. - Patch 2/3: Changed. - Patch 3/3: No change. Patch 1/3 1. Only rename ae3xx as atcpit100. 2. Squashed Kconfig rename ae3xx into this patch to keep things in a consistent state. Patch 2/3 1. Modify function name

[U-Boot] [PATCH v2 2/3] cosmetic: atcpit100_timer: Rename function name as atcpit100

2017-11-26 Thread Andes
From: Rick Chen Integrate function and struct name as atcpit100 will be more reasonable. Signed-off-by: Rick Chen --- drivers/timer/atcpit100_timer.c | 34 +- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git

[U-Boot] [PATCH v2 3/3] dt-bindings: timer: Add andestech atcpit100 timer

2017-11-26 Thread Andes
b/doc/device-tree-bindings/timer/atcpit100_timer.txt @@ -0,0 +1,31 @@ +Andestech ATCPIT100 timer +-- +ATCPIT100 is a generic IP block from Andes Technology, embedded in +Andestech AE3XX, AE250 platforms and other designs. + +This timer i

[U-Boot] [PATCH v2 0/3] Rename ae3xx timer to atcpit100

2017-11-26 Thread Andes
From: Rick Chen Changelog v2 - Patch 1/3: Changed. - Patch 2/3: Changed. - Patch 3/3: No change. Patch 1/3 1. Only rename ae3xx as atcpit100. 2. Squashed Kconfig rename ae3xx into this patch to keep things in a consistent state. Patch 2/3 1. Modify function name

[U-Boot] [PATCH v2 2/3] cosmetic: atcspi200: Rename function name as atcspi200

2017-11-22 Thread Andes
pyright 2017 Andes Technology, Inc. * Author: Rick Chen (r...@andestech.com) @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI1_BASE 0xf0f0 #define NSPI_MAX_CS_NUM1 -struct ae3xx_spi_regs { +struct atcspi200_spi_regs { u32 rev; u32

[U-Boot] [PATCH v2 3/3] dt-bindings: timer: Add andestech atcpit100 timer

2017-11-22 Thread Andes
b/doc/device-tree-bindings/timer/atcpit100_timer.txt @@ -0,0 +1,31 @@ +Andestech ATCPIT100 timer +-- +ATCPIT100 is a generic IP block from Andes Technology, embedded in +Andestech AE3XX, AE250 platforms and other designs. + +This timer i

[U-Boot] [PATCH v2 1/3] ae3xx: timer: Rename AE3XX to ATCPIT100

2017-11-22 Thread Andes
From: Rick Chen ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: Rick Chen --- configs/adp-ae3xx_defconfig| 2 +-

[U-Boot] [PATCH v2 2/3] cosmetic: atcpit100_timer: Rename function name as atcpit100

2017-11-22 Thread Andes
From: Rick Chen Integrate function and struct name as atcpit100 will be more reasonable. Signed-off-by: Rick Chen --- drivers/timer/atcpit100_timer.c | 34 +- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git

[U-Boot] [PATCH v2 1/3] spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi

2017-11-22 Thread Andes
From: Rick Chen atcspi200 is Andestech spi ip which is embedded in AE3XX and AE250 platforms. So rename as atcspi200 will be more reasonable to be used in different platforms. Signed-off-by: Rick Chen --- configs/adp-ae3xx_defconfig

[U-Boot] [PATCH v2 3/3] dt-bindings: spi: Add andestech atcspi200 spi binding doc

2017-11-22 Thread Andes
From: Rick Chen Add a document to describe Andestech atcspi200 spi and binding information. Signed-off-by: Rick Chen --- doc/device-tree-bindings/spi/spi-atcspi200.txt | 37 ++ 1 file changed, 37 insertions(+) create mode 100644

[U-Boot] [PATCH v3 0/4] Rename AE3XX timer to ATCPIT100

2017-11-27 Thread Andes
From: Rick Chen Changelog v3 - Patch 1/4: No change. - Patch 2/4: No change. - Patch 3/4: New. - Patch 4/4: No change. Patch 3/4 1. Use dev_get_platdata to get dev private platdata. Rick Chen (4): ae3xx: timer: Rename AE3XX to ATCPIT100

[U-Boot] [PATCH 2/3] spi: atcspi200: Fix compiler warning

2018-05-22 Thread Andes
From: Rick Chen Fix warning as below when compile in 64-bit. warning: format '%u' expects argument of type 'unsigned int', but argument 6 has type 'size_t {aka long unsigned int} Signed-off-by: Rick Chen Signed-off-by: Rick Chen

[U-Boot] [PATCH 3/3] net: ftmac100: Fix compiler warning

2018-05-22 Thread Andes
From: Rick Chen Fix warnings as below when compile in 64-bit. warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu

[U-Boot] [PATCH 1/3] configs: ax25-ae350: Set 64-bit as default configuration

2018-05-22 Thread Andes
From: Rick Chen Set 64-bit as default configuration for ax25-ae350. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ax25-ae350_defconfig | 1 + 1 file changed, 1 insertion(+)

[U-Boot] [PATCH 1/2] riscv: dts: Sync DT with Linux Kernel

2018-05-23 Thread Andes
From: Rick Chen Use same dts to boot U-Boot and RISC-V Linux Kernel v4.16-rc2 in ax25-ae350 platform. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350.dts | 204

[U-Boot] [PATCH 2/2] mmc: ftsdc010_mci: Sync compatible with DT mmc node

2018-05-23 Thread Andes
From: Rick Chen The compatible string of ftsdc010_mci.c is different from the mmc driver in Linux Kernel. Modify it for consistency. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu ---

[U-Boot] [PATCH 4/4] mtd: ftsmc020: Drop unsed code

2018-05-23 Thread Andes
From: Rick Chen ftsmc020_init is not used anymore. So it can be removed. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- drivers/mtd/Makefile | 1 - drivers/mtd/ftsmc020.c | 38

[U-Boot] [PATCH 3/4] board: ax25-ae350: Support cfi flash

2018-05-23 Thread Andes
From: Rick Chen Add smc_init() to get register base from dts and deal with atfsmc020 controler initialzation job. Write protect is enabled by default. So WP shall be disabled when startup, then cfi flash can be detected and erasing and writing can be executed. Adp-ae3xx and

[U-Boot] [PATCH 2/4] riscv: dts: Support cfi flash

2018-05-23 Thread Andes
From: Rick Chen Add nor node for cfi-flash driver and smc node for smc(aftsmc020) controller. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350.dts | 12

[U-Boot] [PATCH 1/4] configs: ax25-ae350: Support cfi flash

2018-05-23 Thread Andes
From: Rick Chen Enable cfi flash driver and setup flash parameters to support parallel nor flash which type is JS28F00A-M29EWH. Verification: Size detection, data read, erase and write are all ok. Signed-off-by: Rick Chen Signed-off-by: Rick Chen

[U-Boot] [PATCH 1/4] riscv: cpu: nx25: Rename as ax25

2018-05-22 Thread Andes
From: Rick Chen <r...@andestech.com> Andes has rearranged the product combinations. nx25 and ax25 both are RISC-V architecture cpu core. But ax25 has MMU unit inside, and nx25 is not. Cpu nx25 and platform ae250 are arranged in pairs. Cpu ax25 and platform ae350 are arranged in

[U-Boot] [PATCH 4/4] doc: ae250: Rename as ae350

2018-05-22 Thread Andes
s(-) create mode 100644 doc/README.AX25 delete mode 100644 doc/README.NX25 delete mode 100644 doc/README.ae250 create mode 100644 doc/README.ae350 diff --git a/doc/README.AX25 b/doc/README.AX25 new file mode 100644 index 000..7a607dd --- /dev/null +++ b/doc/README.AX25 @@ -0,0 +1,46 @@ +AX25

[U-Boot] [PATCH 3/4] configs: nx25-ae250:Rename as ax25-ae350

2018-05-22 Thread Andes
TS=y diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h new file mode 100644 index 000..a90c75a --- /dev/null +++ b/include/configs/ax25-ae350.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <r...@andes

[U-Boot] [PATCH 2/4] board: nx25-ae250: Rename as ax25-ae350

2018-05-22 Thread Andes
/ax25-ae350/Makefile b/board/AndesTech/ax25-ae350/Makefile new file mode 100644 index 000..b8bd8ec --- /dev/null +++ b/board/AndesTech/ax25-ae350/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen, Andes Technology Corporation <r...@andestech.com&g

[U-Boot] [PATCH] travis.yml: Support RISC-V 64-bit

2018-05-30 Thread Andes
From: Rick Chen Fix riscv: ax25-ae350 build fail problem https://travis-ci.org/trini/u-boot/jobs/385147373 ... Building current source for 1 boards (1 thread, 2 jobs per thread) riscv: + ax25-ae350 +arch/riscv/cpu/ax25/start.S: Assembler messages: +arch/riscv/cpu/ax25/start.S:48: Error:

[U-Boot] [PATCH 04/12] riscv: nx25: include: Add header files to support RISC-V

2017-12-22 Thread Andes
420f --- /dev/null +++ b/arch/riscv/include/asm/bitops.h @@ -0,0 +1,172 @@ +/* + * Copyright 1995, Russell King. + * Various bits and pieces copyrights include: + * Linus Torvalds (test_bit). + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <r...

[U-Boot] [PATCH 11/12] riscv: Modify generic codes to support RISC-V

2017-12-22 Thread Andes
From: Rick Chen Support common commands bdinfo and image format, also modify common generic flow for RISC-V. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu --- arch/Kconfig |

[U-Boot] [PATCH 06/12] riscv: board: Add nx25-ae250 to support RISC-V

2017-12-22 Thread Andes
s/nx25-ae250.h +F: configs/nx25-ae250_defconfig diff --git a/board/AndesTech/nx25-ae250/Makefile b/board/AndesTech/nx25-ae250/Makefile new file mode 100644 index 000..66b6814 --- /dev/null +++ b/board/AndesTech/nx25-ae250/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Andes Techno

[U-Boot] [PATCH 05/12] riscv: Add Kconfig to support RISC-V

2017-12-22 Thread Andes
option to build an U-Boot for RISCV64 architecture. + +endchoice + +config 32BIT + bool + +config 64BIT + bool + +endmenu diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile new file mode 100644 index 000..09d24db --- /dev/null +++ b/arch/riscv/Makefile @@ -0,0 +1,11 @@ +# +# C

[U-Boot] [PATCH 03/12] riscv: nx25: dts: Add AE250 dts to support RISC-V

2017-12-22 Thread Andes
From: Rick Chen AE250 is the Soc using NX25 cpu core base on RISC-V arch. Details please see the doc/README.ae250. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu ---

[U-Boot] [PATCH 02/12] riscv: nx25: lib: Add relative lib funcs to support RISC-V

2017-12-22 Thread Andes
/lib/Makefile b/arch/riscv/lib/Makefile new file mode 100644 index 000..323cf3e --- /dev/null +++ b/arch/riscv/lib/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen

[U-Boot] [PATCH 01/12] riscv: cpu: Add nx25 to support RISC-V

2017-12-22 Thread Andes
From: Rick Chen <r...@andestech.com> Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok.

[U-Boot] [PATCH 07/12] riscv: configs: Add nx25-ae250.h to support RISC-V

2017-12-22 Thread Andes
igs/nx25-ae250.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <r...@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * CPU and Board Confi

[U-Boot] [PATCH 12/12] riscv: doc: Add relative doc to describe RISC-V

2017-12-22 Thread Andes
to hold a pointer to the global data + Memory Management: -- diff --git a/doc/README.NX25 b/doc/README.NX25 new file mode 100644 index 000..9f054e5 --- /dev/null +++ b/doc/README.NX25 @@ -0,0 +1,46 @@ +NX25 is Andes CPU IP to adopt RISC-V architecture. + +Features + + +C

[U-Boot] [PATCH 09/12] risck: tools: Prelink u-boot

2017-12-22 Thread Andes
From: Rick Chen Add prelink-riscv to arrange .rela.dyn and .rela.got in compile time. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu --- Makefile|4 ++

[U-Boot] [PATCH 08/12] riscv: defconfig: Add nx25-ae250 defconfig to support RISC-V

2017-12-22 Thread Andes
From: Rick Chen Add nx25-ae250 default configuration for RISC-V Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu --- configs/nx25-ae250_defconfig | 36

[U-Boot] [PATCH 10/12] riscv: Support standalone

2017-12-22 Thread Andes
++ 2 files changed, 53 insertions(+), 0 deletions(-) create mode 100644 examples/standalone/riscv.lds diff --git a/examples/standalone/riscv.lds b/examples/standalone/riscv.lds new file mode 100644 index 000..7d8c482 --- /dev/null +++ b/examples/standalone/riscv.lds @@ -0,0 +1,41 @@

[U-Boot] [PATCH] travis.yml: Support RISC-V

2018-01-11 Thread Andes
From: Rick Chen Enable travis-ci support with a link having built. Signed-off-by: Chih-Mao Chen Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu ---

[U-Boot] [PATCH v2 04/12] riscv: nx25: include: Add header files to support RISC-V

2017-12-25 Thread Andes
scv/include/asm/bitops.h @@ -0,0 +1,172 @@ +/* + * Copyright 1995, Russell King. + * Various bits and pieces copyrights include: + * Linus Torvalds (test_bit). + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <r...@andestech.com> + * + * bi

[U-Boot] [PATCH v2 05/12] riscv: Add Kconfig to support RISC-V

2017-12-25 Thread Andes
32BIT + bool + +config 64BIT + bool + +endmenu diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile new file mode 100644 index 000..09d24db --- /dev/null +++ b/arch/riscv/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen, Andes Technology

[U-Boot] [PATCH v2 01/12] riscv: cpu: Add nx25 to support RISC-V

2017-12-25 Thread Andes
From: Rick Chen <r...@andestech.com> Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok.

[U-Boot] [PATCH v2 00/12] Add NX25 to support RISC-V

2017-12-25 Thread Andes
From: Rick Chen Changelog v2: - Patch 5/12 : Changes - Patch 9/12 : Changes - Others : No changed [Patch 5/12] riscv: Add Kconfig to support RISC-V - Modify the top-level MAINTAINERS for RISC-V [Patch 9/12] riscv: tools: Prelink u-boot - Add license

[U-Boot] [PATCH v2 02/12] riscv: nx25: lib: Add relative lib funcs to support RISC-V

2017-12-25 Thread Andes
ch/riscv/lib/Makefile new file mode 100644 index 000..323cf3e --- /dev/null +++ b/arch/riscv/lib/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen, Andes Technology C

[U-Boot] [PATCH v2 03/12] riscv: nx25: dts: Add AE250 dts to support RISC-V

2017-12-25 Thread Andes
From: Rick Chen AE250 is the Soc using NX25 cpu core base on RISC-V arch. Details please see the doc/README.ae250. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu ---

[U-Boot] [PATCH v2 06/12] riscv: board: Add nx25-ae250 to support RISC-V

2017-12-25 Thread Andes
configs/nx25-ae250_defconfig diff --git a/board/AndesTech/nx25-ae250/Makefile b/board/AndesTech/nx25-ae250/Makefile new file mode 100644 index 000..66b6814 --- /dev/null +++ b/board/AndesTech/nx25-ae250/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen,

[U-Boot] [PATCH v2 11/12] riscv: Modify generic codes to support RISC-V

2017-12-25 Thread Andes
From: Rick Chen Support common commands bdinfo and image format, also modify common generic flow for RISC-V. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu Reviewed-by: Tom Rini

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