Re: [U-Boot] No NAND device found!!! Freescale MPC8544+SAMSUNG 1GB Nand Flash , please help!

2009-09-16 Thread Bin Meng
On Wed, Sep 16, 2009 at 5:40 AM, duckycool duckyc...@gmail.com wrote:   Correction, the nand flash is K9F8G08U0M. K9F8G08U0M is a 4KB page size NAND flash. Freescale eLBC NAND flash controller does not support 4KB page size. thanks bmeng ___ U-Boot

Re: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC Controller Driver

2009-09-27 Thread Bin Meng
add a comment before the udelay? Regards, Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC Controller Driver

2009-10-05 Thread Bin Meng
transfer complete *\ Is that ok ?? Sure, adding a comment line would help a lot. Regards, Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/2] x86: Fix rom version build with CONFIG_X86_RESET_VECTOR

2014-10-16 Thread Bin Meng
When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking process misses the resetvec.o and start16.o so it cannot generate the rom version of U-Boot. The top level Makefile is updated to pull them into the final linking process. Signed-off-by: Bin Meng bmeng...@gmail.com --- Makefile | 1

[U-Boot] [PATCH 2/2] x86: Fix GDT limit in start16.S

2014-10-16 Thread Bin Meng
GDT limit should be one less than an integral multiple of eight. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/cpu/start16.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 8b9b327..6968fda 100644 --- a/arch/x86

Re: [U-Boot] [PATCH 1/2] x86: Fix rom version build with CONFIG_X86_RESET_VECTOR

2014-10-16 Thread Bin Meng
Hi Simon, On Thu, Oct 16, 2014 at 6:13 PM, Simon Glass s...@chromium.org wrote: Can we please do this in rch/x86/cpu/Makefile instead? Something like: extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o obj-y += interrupts.o cpu.o obj-$(CONFIG_PCI) += pci.o Regards,

[U-Boot] [PATCH v2 2/2] x86: Fix GDT limit in start16.S

2014-10-16 Thread Bin Meng
GDT limit should be one less than an integral multiple of eight. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/cpu/start16.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 8b9b327..6968fda 100644 --- a/arch/x86

[U-Boot] [PATCH v2 1/2] x86: Fix rom version build with CONFIG_X86_RESET_VECTOR

2014-10-16 Thread Bin Meng
When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking process misses the resetvec.o and start16.o so it cannot generate the rom version of U-Boot. The arch/x86/cpu/Makefile is updated to pull them into the final linking process. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86

[U-Boot] [PATCH] common/cmd_io.c: Fix incorrect help for iod/iow

2014-10-20 Thread Bin Meng
Signed-off-by: Bin Meng bmeng...@gmail.com --- common/cmd_io.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cmd_io.c b/common/cmd_io.c index eefac36..c59148f 100644 --- a/common/cmd_io.c +++ b/common/cmd_io.c @@ -70,8 +70,8 @@ int do_io_iow(cmd_tbl_t *cmdtp

Re: [U-Boot] [PATCH] common/cmd_io.c: Fix incorrect help for iod/iow

2014-10-20 Thread Bin Meng
Hi Simon, On Tue, Oct 21, 2014 at 12:46 AM, Simon Glass s...@chromium.org wrote: Hi Bin, Are you using the coreboot support? What board are you using? Not coreboot, but U-Boot directly booting from reset vector on Intel Crown Bay board. Regards, Bin

Re: [U-Boot] [PATCH] common/cmd_io.c: Fix incorrect help for iod/iow

2014-10-20 Thread Bin Meng
Hi Simon, On Tue, Oct 21, 2014 at 9:34 AM, Simon Glass s...@chromium.org wrote: Hi Bin, OK I see - interesting! I talked with Wolfgang at the mini-Summit last week about a bare x86 port and he seemed keen on the idea. So I've been taking a look. I was planning to use the Minnowboard Max, but

[U-Boot] [PATCH 0/5] spi: sf: ICH SPI driver fix and SST25* changes

2014-10-23 Thread Bin Meng
can only test the ICH SPI driver with an ICH 7 compatible chipset. ICH 9 should work and it is appreciated if you could help testing and confirm it really does not break anything. Bin Meng (5): spi/ich.c: Fix a bug of reading from a non-64 bytes aligned address spi/ich.c: Set the rx operation

[U-Boot] [PATCH 1/5] spi/ich.c: Fix a bug of reading from a non-64 bytes aligned address

2014-10-23 Thread Bin Meng
devices. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/spi/ich.c | 17 ++--- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index f5c6f3e..c4d3a29 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -483,8 +483,6 @@ int

[U-Boot] [PATCH 2/5] spi/ich.c: Set the rx operation mode for ich 7

2014-10-23 Thread Bin Meng
ICH 7 SPI controller only supports array read command (03h). Fast array read command (0Bh) is not supported. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/spi/ich.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index c4d3a29..b356411

[U-Boot] [PATCH 3/5] spi: sf: Support byte program for sst spi flash

2014-10-23 Thread Bin Meng
to be used. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi/sf_internal.h | 2 ++ drivers/mtd/spi/sf_ops.c | 31 +++ drivers/mtd/spi

[U-Boot] [PATCH 4/5] sf: Update SST25* flash params of supported read commands

2014-10-23 Thread Bin Meng
Explicitly list supported read commands in the flash prarmas table for SST25* flash parts. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi/sf_params.c | 20 ++-- include/spi_flash.h | 3 ++- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git

[U-Boot] [PATCH 5/5] sf: Update SST25* flash params of sector size numbers

2014-10-23 Thread Bin Meng
Change SST25* flash sector size to 4KiB to match SECT_4K. This makes 'sf erase offset +len' work on real 4KiB boundary instead of 64KiB. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi/sf_params.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff

Re: [U-Boot] [PATCH 4/5] sf: Update SST25* flash params of supported read commands

2014-10-27 Thread Bin Meng
Hi Jegan, On Tue, Oct 28, 2014 at 2:08 AM, Jagan Teki jagannadh.t...@gmail.com wrote: What is this, by defining RD_EXTN the fastest read cmd will pick based on controller mode_rx Why this RD_SLOW again? does this means the specific flash part will only support slow read? Correct, the SST25*

Re: [U-Boot] [PATCH 3/5] spi: sf: Support byte program for sst spi flash

2014-10-27 Thread Bin Meng
Hi Jegan, On Tue, Oct 28, 2014 at 2:00 AM, Jagan Teki jagannadh.t...@gmail.com wrote: I believe byte write is already been used within the sst_write_wp - please check. Yes, byte write is used within sst_write_wp, however that does not mean sst_write_wp is doing the correct thing for byte

Re: [U-Boot] [PATCH 4/5] sf: Update SST25* flash params of supported read commands

2014-10-28 Thread Bin Meng
Hi Jagan, On Tue, Oct 28, 2014 at 3:09 PM, Jagan Teki jagannadh.t...@gmail.com wrote: Hi Bin, On 28 October 2014 06:52, Bin Meng bmeng...@gmail.com wrote: Hi Jegan, On Tue, Oct 28, 2014 at 2:08 AM, Jagan Teki jagannadh.t...@gmail.com wrote: What is this, by defining RD_EXTN the fastest

Re: [U-Boot] [PATCH 4/5] sf: Update SST25* flash params of supported read commands

2014-10-28 Thread Bin Meng
see below. On 28 October 2014 14:08, Bin Meng bmeng...@gmail.com wrote: I am not sure if I understand it correctly. Do you mean adding ARRAY_FAST to: enum spi_read_cmds { ARRAY_SLOW = 1 0, DUAL_OUTPUT_FAST= 1 1, DUAL_IO_FAST= 1 2

Re: [U-Boot] [PATCH 4/5] sf: Update SST25* flash params of supported read commands

2014-10-29 Thread Bin Meng
Hi Jagan, On Wed, Oct 29, 2014 at 2:16 PM, Jagan Teki jagannadh.t...@gmail.com wrote: Hi Bin, This looks odd to me - supporting array slow without support on fast read. Please check the datasheets, and as per as my knowledge/experience it should support both. It is not the flash but the

[U-Boot] [PATCH v2 00/12] spi: sf: ICH SPI driver fix and flash params update

2014-11-01 Thread Bin Meng
: - Rebased to u-boot-spi/mater. - Reviewed and updated the params of all currently supported flash parts per their datasheets. - Corrected AT25DF321 JEDEC ID. - Corrected Atmel bulk erase command to 50h instead of D8h. - Added AT25DF321A, W25X10, W25X20, W25X80 params. Bin Meng (12): spi

[U-Boot] [PATCH v2 01/12] spi/ich.c: Fix a bug of reading from a non-64 bytes aligned address

2014-11-01 Thread Bin Meng
devices. Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org --- drivers/spi/ich.c | 17 ++--- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index f5c6f3e

[U-Boot] [PATCH v2 02/12] spi/ich.c: Set the rx operation mode for ich 7

2014-11-01 Thread Bin Meng
ICH 7 SPI controller only supports array read command (03h). Fast array read command (0Bh) is not supported. Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org --- drivers/spi/ich.c | 4 1 file changed, 4 insertions

[U-Boot] [PATCH v2 03/12] spi: sf: Support byte program for sst spi flash

2014-11-01 Thread Bin Meng
to be used. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org --- drivers/mtd/spi/sf_internal.h | 2 ++ drivers/mtd

[U-Boot] [PATCH v2 07/12] sf: Update GigaDevice flash params

2014-11-01 Thread Bin Meng
Explicitly list supported read commands in the flash prarmas table for GigaDevice flash parts. Update flash sector size to 4KiB as long as flash supports sector erase (20h) command. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi/sf_params.c | 4 ++-- 1 file changed, 2 insertions

[U-Boot] [PATCH v2 06/12] sf: Update EON flash params

2014-11-01 Thread Bin Meng
Explicitly list supported read commands in the flash prarmas table for EON flash parts. Update flash sector size to 4KiB as long as flash supports sector erase (20h) command. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi/sf_params.c | 8 1 file changed, 4 insertions

[U-Boot] [PATCH v2 04/12] sf: Update SST flash params

2014-11-01 Thread Bin Meng
Explicitly list supported read commands in the flash prarmas table for SST flash parts. Also change flash sector size to 4KiB to match SECT_4K. This makes 'sf erase offset +len' work on real 4KiB boundary instead of 64KiB. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi

[U-Boot] [PATCH v2 05/12] sf: Update Atmel flash params

2014-11-01 Thread Bin Meng
. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi/sf_internal.h | 5 + drivers/mtd/spi/sf_params.c | 17 + drivers/mtd/spi/sf_probe.c| 4 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi

[U-Boot] [PATCH v2 10/12] sf: Update Micron flash params

2014-11-01 Thread Bin Meng
Explicitly list supported read commands in the flash prarmas table for Micron flash parts. Update flash sector size to 4KiB as long as flash supports sector erase (20h) command. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi/sf_params.c | 46

[U-Boot] [PATCH v2 08/12] sf: Update Macronix flash params

2014-11-01 Thread Bin Meng
Explicitly list supported read commands in the flash prarmas table for Macronix flash parts. Update flash sector size to 4KiB as long as flash supports sector erase (20h) command. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi/sf_params.c | 20 ++-- 1 file changed

[U-Boot] [PATCH v2 11/12] sf: Update Winbond flash params

2014-11-01 Thread Bin Meng
Explicitly list supported read commands in the flash prarmas table for Winbond flash parts. Update flash sector size to 4KiB as long as flash supports sector erase (20h) command. Add W25X10, W25X20, W25X80 params per datasheet. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi

[U-Boot] [PATCH v2 12/12] sf: Give proper spacing between flash table params

2014-11-01 Thread Bin Meng
Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi/sf_params.c | 188 ++-- 1 file changed, 95 insertions(+), 93 deletions(-) diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 7818913..601ab31 100644 --- a/drivers/mtd

[U-Boot] [PATCH v2 09/12] sf: Update Spansion flash params

2014-11-01 Thread Bin Meng
Explicitly list supported read commands in the flash prarmas table for Spansion flash parts. Update flash sector size to 4KiB as long as flash supports sector erase (20h) command. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/mtd/spi/sf_params.c | 20 ++-- 1 file changed

[U-Boot] [RFC] x86: Intel FSP integration

2014-11-02 Thread Bin Meng
Hi Simon, I am preparing patches for my U-Boot port on Intel Crown Bay CRB which uses Intel FSP for the memory and chipset initialization. Intel FSP is a binary blob inside which 3 pre-defined entry pointes are available for 3rd party bootloader to call to perform various jobs at different

Re: [U-Boot] [RFC] x86: Intel FSP integration

2014-11-03 Thread Bin Meng
Hi Simon, Thanks for the comments. On Tue, Nov 4, 2014 at 10:09 AM, Simon Glass s...@chromium.org wrote: Hi Bin, Well it's certainly not ideal but from what I can tell these blobs are a fact of life on Intel machines still. For the ivybridge stuff, I've found I need a microcode blob, a

[U-Boot] [PATCH 2/4] x86: Do TSC MSR calibration only for known/supported CPUs

2014-11-04 Thread Bin Meng
Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on processors which do not have this MSR. Instead only doing the MSR calibration for known/supported CPUs. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/lib/tsc_timer.c | 116

[U-Boot] [PATCH 1/4] x86: Display more detailed CPU information on boot

2014-11-04 Thread Bin Meng
happens in x86_cpu_init_f() and corresponding fields are saved in the global data. Later print_cpuinfo() just uses these fields to display CPU information without the need to probe again in real time. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/cpu/cpu.c | 282

[U-Boot] [PATCH 3/4] x86: Add quick TSC calibration via PIT

2014-11-04 Thread Bin Meng
Use the same way that Linux does for quick TSC calibration via PIT when calibration via MSR fails. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/include/asm/i8254.h | 3 + arch/x86/lib/tsc_timer.c | 155 +++ 2 files changed, 158 insertions

[U-Boot] [PATCH 4/4] x86: Save TSC frequency in the global data

2014-11-04 Thread Bin Meng
Return the saved TSC frequency in get_tbclk_mhz(). Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/include/asm/global_data.h | 1 + arch/x86/lib/tsc_timer.c | 4 2 files changed, 5 insertions(+) diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm

Re: [U-Boot] [PATCH v2 00/12] spi: sf: ICH SPI driver fix and flash params update

2014-11-04 Thread Bin Meng
Hi Jagan, On Wed, Nov 5, 2014 at 5:21 AM, Jagan Teki jagannadh.t...@gmail.com wrote: On 1 November 2014 14:23, Bin Meng bmeng...@gmail.com wrote: This series fix several bugs in current ICH SPI driver as well as adding byte program support for the SST25* flash. Flash params are updated

Re: [U-Boot] [PATCH 22/39] x86: Move Coreboot PCI into common cpu area

2014-11-06 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: This code is not really Coreboot-specific, so move it into the common area and rename it. OK, but current coreboot pci codes are broken, thus need to be fixed before making it common. Signed-off-by: Simon Glass

Re: [U-Boot] [PATCH 07/39] x86: Add processor functions for cpuid and stack pointer

2014-11-06 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:19 AM, Simon Glass s...@chromium.org wrote: Add some functions to access cpuid from C in various useful ways. Also add a function to get the stack pointer and another to halt the CPU. Signed-off-by: Simon Glass s...@chromium.org ---

Re: [U-Boot] [PATCH 22/39] x86: Move Coreboot PCI into common cpu area

2014-11-06 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 8:26 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 6 November 2014 17:07, Bin Meng bmeng...@gmail.com wrote: Hi Simon, -static struct pci_config_table pci_coreboot_config_table[] = { +static struct pci_config_table pci_x86_config_table

Re: [U-Boot] [PATCH 22/39] x86: Move Coreboot PCI into common cpu area

2014-11-06 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 9:53 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 6 November 2014 18:39, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Fri, Nov 7, 2014 at 8:26 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 6 November 2014 17:07, Bin Meng bmeng

Re: [U-Boot] [PATCH 08/39] x86: Remove REALMODE_BASE which is no longer used

2014-11-06 Thread Bin Meng
) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm -PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0 PLATFORM_CPPFLAGS += -march=i386 -m32 # Support generic board on x86 -- Reviewed-by: Bin Meng bmeng...@gmail.com ___ U-Boot mailing list U-Boot@lists.denx.de http

Re: [U-Boot] [PATCH 09/39] x86: Remove board_init16() call which is not used

2014-11-06 Thread Bin Meng
) */ + /* Turn off cache (this might require a 486-class CPU) */ movl%cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl%eax, %cr0 -- Reviewed-by: Bin Meng bmeng...@gmail.com ___ U-Boot mailing list U-Boot

Re: [U-Boot] [PATCH 10/39] x86: Remove unused early_board_init() call

2014-11-06 Thread Bin Meng
-Identifier:GPL-2.0+ - */ - -/* board early intialization */ -.globl early_board_init -early_board_init: - /* No 32-bit board specific initialisation */ - jmp early_board_init_ret -- Reviewed-by: Bin Meng bmeng...@gmail.com ___ U-Boot

Re: [U-Boot] [PATCH 11/39] x86: Invalidate TLB as early as possible

2014-11-06 Thread Bin Meng
, %ebx + xorl%eax, %eax + movl%eax, %cr3/* Invalidate TLB */ + /* Turn off cache (this might require a 486-class CPU) */ movl%cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax -- Reviewed-by: Bin Meng bmeng...@gmail.com

Re: [U-Boot] [PATCH 12/39] x86: Tidy up global descriptor table setup

2014-11-07 Thread Bin Meng
- movw%bx, %ax /* Enter, U-boot! */ callboard_init_f -- Reviewed-by: Bin Meng bmeng...@gmail.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 13/39] x86: Use the standard dram_init() function

2014-11-07 Thread Bin Meng
, /* TODO: unify all these dram functions? */ -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_X86) dram_init, /* configure available RAM banks */ #endif #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) -- Reviewed-by: Bin Meng bmeng...@gmail.com

Re: [U-Boot] [PATCH 14/39] x86: Use the standard arch_cpu_init() function

2014-11-07 Thread Bin Meng
-by: Bin Meng bmeng...@gmail.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 15/39] x86: Remove unnecessary find_fdt() function

2014-11-07 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: This is no-longer needed so drop it. Signed-off-by: Simon Glass s...@chromium.org --- arch/x86/include/asm/init_helpers.h | 1 - common/board_f.c| 5 - 2 files changed, 6 deletions(-)

Re: [U-Boot] [PATCH 16/39] x86: Fix up some missing prototypes

2014-11-07 Thread Bin Meng
total_size); +void dram_init_banksize(void); + void setup_pcat_compatibility(void); void isa_unmap_rom(u32 addr); -- Reviewed-by: Bin Meng bmeng...@gmail.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 17/39] x86: Add chromebook_link board

2014-11-07 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of

Re: [U-Boot] [PATCH 18/39] x86: Save the BIST value on reset

2014-11-07 Thread Bin Meng
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base)); #endif +#ifdef CONFIG_X86 + DEFINE(GD_BIST, offsetof(struct global_data, arch.bist)); +#endif #if defined(CONFIG_ARM) -- Reviewed-by: Bin Meng bmeng...@gmail.com ___ U-Boot

Re: [U-Boot] [PATCH 20/39] x86: Emit post codes in startup code

2014-11-07 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post

Re: [U-Boot] [PATCH 21/39] x86: chromebook_link: Implement CAR support (cache as RAM)

2014-11-07 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass

Re: [U-Boot] [PATCH 06/39] x86: config: Move common x86 configs to a common file

2014-11-07 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:19 AM, Simon Glass s...@chromium.org wrote: Many of the x86 CONFIG options will be common across different boards. Move them to a common file. Signed-off-by: Simon Glass s...@chromium.org --- include/configs/coreboot.h | 289

Re: [U-Boot] [PATCH 1/4] x86: Display more detailed CPU information on boot

2014-11-08 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 10:22 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 4 November 2014 07:58, Bin Meng bmeng...@gmail.com wrote: Currently only basic CPU information (x86 or x86_64) is displayed on boot. This commit adds more detailed information output including CPU

Re: [U-Boot] [PATCH 1/4] x86: Display more detailed CPU information on boot

2014-11-08 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 10:23 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 6 November 2014 19:22, Simon Glass s...@chromium.org wrote: Hi Bin, On 4 November 2014 07:58, Bin Meng bmeng...@gmail.com wrote: Currently only basic CPU information (x86 or x86_64) is displayed

[U-Boot] [PATCH v2 1/4] x86: Do CPU identification in the early phase

2014-11-09 Thread Bin Meng
The CPU identification happens in x86_cpu_init_f() and corresponding fields are saved in the global data for later use. Signed-off-by: Bin Meng bmeng...@gmail.com --- Changes for v2: - Update the patch per review comments from Simon Glass - cpu_vendor_name() and fill_processor_name

[U-Boot] [PATCH v2 4/4] x86: Save TSC frequency in the global data

2014-11-09 Thread Bin Meng
Return the saved TSC frequency in get_tbclk_mhz(). Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org --- arch/x86/include/asm/global_data.h | 1 + arch/x86/lib/tsc_timer.c | 4 2 files changed, 5 insertions

[U-Boot] [PATCH v2 2/4] x86: Do TSC MSR calibration only for known/supported CPUs

2014-11-09 Thread Bin Meng
Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on processors which do not have this MSR. Instead only doing the MSR calibration for known/supported CPUs. Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org

[U-Boot] [PATCH v2 3/4] x86: Add quick TSC calibration via PIT

2014-11-09 Thread Bin Meng
Use the same way that Linux does for quick TSC calibration via PIT when calibration via MSR fails. Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org --- arch/x86/include/asm/i8254.h | 3 + arch/x86/lib/tsc_timer.c | 155

Re: [U-Boot] [PATCH 31/39] x86: ivybridge: Check BIST value on boot

2014-11-09 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass s...@chromium.org --- arch/x86/cpu/ivybridge/cpu.c | 16

Re: [U-Boot] [PATCH 32/39] x86: ivybridge: Perform Intel microcode update on boot

2014-11-09 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass s...@chromium.org --- arch/x86/cpu/ivybridge/Makefile | 1 +

Re: [U-Boot] [PATCH 33/39] RFC: x86: dts: Add microcode updates for ivybridge CPU

2014-11-09 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Add two microcode updates that are provided for this CPU. The updates have been converted to a device tree form. (The license needs to be converted to SPDX) Signed-off-by: Simon Glass s...@chromium.org ---

Re: [U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init

2014-11-09 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary

Re: [U-Boot] [PATCH 19/39] x86: Build a .rom file which can be flashed to an x86 machine

2014-11-09 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: On x86 machines U-Boot needs to be added to a large ROM image which is then flashed onto the target board. The ROM has a particular format so it makes sense for U-Boot to build this image automatically.

Re: [U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init

2014-11-09 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary

Re: [U-Boot] [PATCH v2 1/4] x86: Do CPU identification in the early phase

2014-11-11 Thread Bin Meng
Hi Simon, On Tue, Nov 11, 2014 at 2:53 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 9 November 2014 07:18, Bin Meng bmeng...@gmail.com wrote: The CPU identification happens in x86_cpu_init_f() and corresponding fields are saved in the global data for later use. Signed-off-by: Bin

Re: [U-Boot] [PATCH v2 2/4] x86: Do TSC MSR calibration only for known/supported CPUs

2014-11-11 Thread Bin Meng
Hi Simon, On Tue, Nov 11, 2014 at 2:54 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 9 November 2014 07:19, Bin Meng bmeng...@gmail.com wrote: Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on processors which do not have this MSR. Instead only doing the MSR

Re: [U-Boot] [PATCH 19/39] x86: Build a .rom file which can be flashed to an x86 machine

2014-11-11 Thread Bin Meng
Hi Simon, On Tue, Nov 11, 2014 at 8:28 AM, Simon Glass s...@chromium.org wrote: Hi Bin, [snip] + $(srctree)/board/$(BOARDDIR)/descriptor.bin I don't see where the descriptor.bin is created? This needs to be downloaded and provided, as with mrc.bin, etc. I thought the

Re: [U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init

2014-11-11 Thread Bin Meng
Hi Simon, On Tue, Nov 11, 2014 at 8:29 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 9 November 2014 23:49, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Implement SDRAM init using the Memory Reference Code (mrc.bin

Re: [U-Boot] [PATCH v2 06/33] x86: config: Move common x86 configs to a common file

2014-11-11 Thread Bin Meng
CONFIG_BOOTP_HOSTNAME + +#define CONFIG_CMD_USB + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_STD_DEVICES_SETTINGS + +#endif /* __CONFIG_H */ -- Reviewed-by: Bin Meng bmeng...@gmail.com Regards, Bin ___ U-Boot mailing list U-Boot

Re: [U-Boot] [PATCH v2 07/33] x86: Add processor functions to halt and get stack pointer

2014-11-11 Thread Bin Meng
Reviewed-by: Bin Meng bmeng...@gmail.com On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote: Add a function to get the stack pointer and another to halt the CPU. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: - Remove the cpuid functions since they were

Re: [U-Boot] [PATCH v2 08/33] x86: Remove unnecessary find_fdt(), prepare_fdt() functions

2014-11-11 Thread Bin Meng
CONFIG_OF_CONTROL fdtdec_check_fdt, -- Reviewed-by: Bin Meng bmeng...@gmail.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 09/33] x86: Replace fill_processor_name() with cpu_get_name()

2014-11-11 Thread Bin Meng
the start + * of @name + * \0 terminator */ -void fill_processor_name(char *processor_name); +char *cpu_get_name(char *name); /** * cpu_call64() - Jump to a 64-bit Linux kernel (internal function) -- Reviewed-by: Bin Meng bmeng...@gmail.com ___ U

Re: [U-Boot] [PATCH v2 10/33] x86: Tidy up timer code for Intel core architecture

2014-11-11 Thread Bin Meng
Hi Simon, On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote: We can use an MSR to obtain the time base. Add this back in and consolidate the code. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: - Add new patch to tidy up timer code for Intel core

Re: [U-Boot] [PATCH v2 13/33] x86: Emit post codes in startup code for Chromebooks

2014-11-11 Thread Bin Meng
Hi Simon, On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote: On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post

Re: [U-Boot] [PATCH v2 15/33] x86: Refactor PCI to permit alternate init

2014-11-11 Thread Bin Meng
Hi Simon, On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote: We want access PCI earlier in the init sequence, so refactor the code so that it does not require use of a BSS variable to work. This will allow us to use early malloc() to store information about a PCI hose.

Re: [U-Boot] [PATCH v2 32/33] x86: ivybridge: Implement SDRAM init

2014-11-11 Thread Bin Meng
Hi Simon, I am not sure if there is anything I missed but when I look at the u-boot-x86/working, the repo content does not match the patch v2 here. And seems you missed my previous comments @

Re: [U-Boot] [PATCH 34/39] x86: ivybridge: Add early init for PCH devices

2014-11-11 Thread Bin Meng
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass s...@chromium.org --- arch/x86/cpu/ivybridge/Makefile | 1

Re: [U-Boot] [PATCH v2 2/4] x86: Do TSC MSR calibration only for known/supported CPUs

2014-11-11 Thread Bin Meng
Hi Simon, On Wed, Nov 12, 2014 at 12:10 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 11 November 2014 01:25, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Tue, Nov 11, 2014 at 2:54 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 9 November 2014 07:19, Bin Meng bmeng

Re: [U-Boot] [PATCH 19/39] x86: Build a .rom file which can be flashed to an x86 machine

2014-11-11 Thread Bin Meng
Hi Simon, On Wed, Nov 12, 2014 at 12:11 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 11 November 2014 01:37, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Tue, Nov 11, 2014 at 8:28 AM, Simon Glass s...@chromium.org wrote: Hi Bin, [snip] + $(srctree)/board

Re: [U-Boot] [PATCH v2 10/33] x86: Tidy up timer code for Intel core architecture

2014-11-11 Thread Bin Meng
Hi Simon, On Wed, Nov 12, 2014 at 12:12 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 11 November 2014 03:05, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote: We can use an MSR to obtain the time base. Add this back

Re: [U-Boot] [PATCH 34/39] x86: ivybridge: Add early init for PCH devices

2014-11-11 Thread Bin Meng
Hi Simon, On Wed, Nov 12, 2014 at 12:15 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 11 November 2014 07:52, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Many PCH devices are hard-coded to a particular PCI address

Re: [U-Boot] [PATCH v2 32/33] x86: ivybridge: Implement SDRAM init

2014-11-11 Thread Bin Meng
Hi Simon, On Wed, Nov 12, 2014 at 12:18 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 11 November 2014 07:37, Bin Meng bmeng...@gmail.com wrote: Hi Simon, I am not sure if there is anything I missed but when I look at the u-boot-x86/working, the repo content does not match the patch

Re: [U-Boot] [PATCH v2 15/33] x86: Refactor PCI to permit alternate init

2014-11-11 Thread Bin Meng
Hi Simon, On Wed, Nov 12, 2014 at 9:02 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 11 November 2014 07:14, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote: We want access PCI earlier in the init sequence, so refactor

Re: [U-Boot] [PATCH v2 00/12] spi: sf: ICH SPI driver fix and flash params update

2014-11-11 Thread Bin Meng
Hi Jagan, On Wed, Nov 5, 2014 at 10:56 AM, Bin Meng bmeng...@gmail.com wrote: Hi Jagan, On Wed, Nov 5, 2014 at 5:21 AM, Jagan Teki jagannadh.t...@gmail.com wrote: On 1 November 2014 14:23, Bin Meng bmeng...@gmail.com wrote: This series fix several bugs in current ICH SPI driver as well

Re: [U-Boot] [PATCH 05/33] x86: Remove board_early_init_r()

2014-11-11 Thread Bin Meng
+21,6 @@ #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 #define CONFIG_SYS_X86_START16 0xf800 #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_DISPLAY_CPUINFO #define CONFIG_X86_RESET_VECTOR -- Reviewed-by: Bin Meng bmeng

Re: [U-Boot] [PATCH 06/33] x86: Panic if there is not relocation data

2014-11-11 Thread Bin Meng
= (Elf32_Addr *)re_src-r_offset; -- Reviewed-by: Bin Meng bmeng...@gmail.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 07/33] x86: Ensure that all relocation data is included in the image

2014-11-11 Thread Bin Meng
On Wed, Nov 12, 2014 at 8:17 AM, Simon Glass s...@chromium.org wrote: Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot. Signed-off-by: Simon Glass s...@chromium.org ---

Re: [U-Boot] [PATCH 07/33] x86: Ensure that all relocation data is included in the image

2014-11-11 Thread Bin Meng
Hi Simon, On Wed, Nov 12, 2014 at 1:28 PM, Simon Glass s...@chromium.org wrote: Hi Bin, On 11 November 2014 22:21, Bin Meng bmeng...@gmail.com wrote: On Wed, Nov 12, 2014 at 8:17 AM, Simon Glass s...@chromium.org wrote: Some toolchains put the relocation data into separate sections. Adjust

Re: [U-Boot] [PATCH 09/33] x86: Factor out common values in the link script

2014-11-11 Thread Bin Meng
Hi Simon, On Wed, Nov 12, 2014 at 8:17 AM, Simon Glass s...@chromium.org wrote: Define the reset base in config.mk so that it does not need to be calculated twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values to fit with this new approach. Signed-off-by: Simon Glass

Re: [U-Boot] [PATCH 08/33] WIP: x86: Drop u-boot.srec from the Makefile

2014-11-11 Thread Bin Meng
Hi Simon, On Wed, Nov 12, 2014 at 8:17 AM, Simon Glass s...@chromium.org wrote: This is not needed on x86 and creates a 4GB file due to the addressing used on x86. This needs to be investigated. This is due to your patch [09/33] x86: Factor out common values in the link script (see

Re: [U-Boot] [PATCH 10/33] rtc: mc146818: Set up RTC at start of day

2014-11-11 Thread Bin Meng
Hi Simon, On Wed, Nov 12, 2014 at 8:17 AM, Simon Glass s...@chromium.org wrote: If the RTC needs to be cleared, write the U-Boot build date to it. In any case make sure the settings are correct. Signed-off-by: Simon Glass s...@chromium.org --- drivers/rtc/mc146818.c | 49

Re: [U-Boot] [PATCH 12/33] x86: pci: Add handlers before and after a PCI hose scan

2014-11-11 Thread Bin Meng
(struct pci_controller *hose); +int board_pci_post_scan(struct pci_controller *hose); + /* * Simple PCI access routines - these work from either the early PCI hose * or the 'real' one, created after U-Boot has memory available -- Reviewed-by: Bin Meng bmeng...@gmail.com

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