Hello,
AMCC PPC460EX canyonlands board with an FPGA PCIe end point:
u-boot sees the end point, but Linux does not:
U-Boot 1.3.3-00249-ga524e11 (Jun 30 2008 - 16:05:51)
CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz)
<...>
Board: Canyonlands - AMCC PPC460EX Evaluation
Hello all,
On Mon, Dec 1, 2008 at 9:12 AM, Benjamin Herrenschmidt
<[EMAIL PROTECTED]> wrote:
> On Fri, 2008-11-28 at 13:50 +0100, Leon Woestenberg wrote:
>>
>> AMCC PPC460EX canyonlands board with an FPGA PCIe end point:
>>
>> u-boot sees the end point, but L
Martijn,
On Fri, Sep 12, 2008 at 8:18 PM, Martijn de Gouw
<[EMAIL PROTECTED]> wrote:
> We have u-boot running on a ixp425 board (pdnb3), without the intel
> stuff.
> The npe binaries are stored seperated in flash, and loaded by u-boot.
> All the code is now gplv2.
>
> We tried to get these patches
Hello,
On Wed, Dec 3, 2008 at 8:40 AM, Trent Piepho <[EMAIL PROTECTED]> wrote:
> On Wed, 3 Dec 2008, Sean MacLennan wrote:
>>> Yes, I would recommend to do it this way if possible. A small NOR for
>>> U-Boot and environment and everything else in NAND. This makes things
>>> much easier. But I unde
Hello,
On Fri, Aug 29, 2008 at 11:19 PM, Wolfgang Denk <[EMAIL PROTECTED]> wrote:
> after some discussions in the past I propose to use the following
> numbering scheme for future releases of U-Boot (starting with the
> ...
> That means the upcoming release, which is scheduled for October
> 2008
--version
powerpc-angstrom-linux-gnuspe-gcc (GCC) 4.3.3
Seems to be a known issue (since 2008-04?!)
Googled some, turns out this patch/workaround works for me on MPC8536DS.
Signed-off-by: Leon Woestenberg
Index: git/cpu/mpc85xx/config.mk
Hello Vadim, Stefan,
On Wed, Jan 14, 2009 at 5:42 PM, vb wrote:
> On Wed, Jan 14, 2009 at 7:03 AM, Stefan Roese wrote:
>> On Tuesday 13 January 2009, vb wrote:
>>
>>> I have several different targets with different PCIe components, but
>>> all using the same base CPU subsystem design, and on som
Hello,
On Wed, Jun 17, 2009 at 1:24 AM, David Hawkins wrote:
>
> I've wired up the COP connection on my board via an FPGA,
> so that I could conceivably use the PowerPC JTAG via
> PCI. However, its the lack of open documentation on the
> JTAG commands that has limited my interest in pursuing
> thi
Hello Stefan,
On Mon, Dec 1, 2008 at 8:46 PM, Stefan Roese wrote:
> On Monday 01 December 2008, Leon Woestenberg wrote:
>> >> Now, if I re-program the end-point FPGA during the u-boot boot
>> >> time-out, Linux will recognize the end-point.
>> >
>>
rgc, char * const argv[])
{
puts ("resetting ...\n");
udelay (5); /* wait 50 ms */
disable_interrupts();
reset_misc();
Thanks,
Leon.
--
Leon Woestenberg
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Hello Maxime, Jagan,
[as I was not subscribed to the u-boot mailing list from this email
address yet, I could not properly reply, nor do I have my
git-send-patch setup yet.]
I tried the patch series and reproduced the sunxi-spl-with-ecc.bin
flow on an A13 Olinuxino board with NAND.
I think the
Hello all,
my two cents on this one:
On Thu, Jan 26, 2017 at 11:08 AM, Bin Meng wrote:
> >> On Wed, Jan 25, 2017 at 1:25 PM, Gregory Fong
> >> wrote:
> >> > I've been looking through the book I have on PCI and through various
> online
> >> > resources, and haven't been able to find evidence th
On Thu, Jan 26, 2017 at 2:19 PM, Gregory Fong
wrote:
> It looks like the main problem is that
> struct pci_device_id with vendor and device both 0 is being used to
> indicate the end of an array. Not that complicated to change, but it
> isn't trivial either, so figure it's best to leave for a f
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