On 23/05/13 11:52, Albert ARIBAUD wrote:
Hi Andre,
On Mon, 6 May 2013 15:17:45 +0200, Andre Przywara
andre.przyw...@linaro.org wrote:
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state.
Introduce a monitor handler routine which
On 2013-07-30 18:07, Alexander Spyridakis wrote:
Hi Alexander,
Since there was much interest, as of late, to see KVM/ARM running on
Samsung's Exynos5250 Chromebook, and given the fact that we are not
aware
of any current work done on this, we take the opportunity to inform
you
that you can
On 12/02/14 08:36, Albert ARIBAUD wrote:
Hi Albert,
On Thu, 12 Dec 2013 11:47:31 +0100, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Marc,
On Sat, 7 Dec 2013 11:19:12 +, Marc Zyngier marc.zyng...@arm.com
wrote:
The current non-sec switching code suffers from one major issue
Hi Albert,
On 13/02/14 10:11, Albert ARIBAUD wrote:
Hi Marc,
On Sat, 7 Dec 2013 11:19:05 +, Marc Zyngier marc.zyng...@arm.com
wrote:
PSCI is an ARM standard that provides a generic interface that
supervisory software can use to manage power in the following
situations:
- Core idle
CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/configs/sun7i.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include
Move the B and D SRAM bank to their actual location (or at least
where the documentation pretends they are).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/include/asm/arch-sunxi/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm
Having the switch to non-secure in the prep phase is causing
all kind of troubles, as that stage can be called multiple times.
Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/lib/bootm-fdt.c | 2 +-
arch/arm/lib/bootm.c | 2 +-
common/image-fdt.c | 7 +--
include/common.h | 6 +++---
4 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib
In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.
Nothing is using it just yet.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/config.mk | 2 +-
arch/arm/cpu/u-boot.lds | 30
In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.
Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/include/asm/proc-armv
primitive.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 161 +++
arch/arm/cpu/armv7/virt-v7.c | 59 +-
arch/arm/include/asm/armv7.h | 10 ++-
arch/arm/include/asm/secure.h| 26 +++
arch/arm/lib
to a generic FDT fixup function
Marc Zyngier (12):
ARM: HYP/non-sec: move switch to non-sec to the last boot phase
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
ARM: non-sec: reset CNTVOFF to zero
ARM: add missing HYP mode constant
ARM: HYP/non-sec: add separate section for secure
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/Makefile | 4 ++
arch/arm/cpu/armv7/psci.S | 105
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...
Signed-off-by: Marc Zyngier marc.zyng
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu
Allow the switch to a second stage secure monitor just before
switching to non-secure.
This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch
Generate the PSCI node in the device tree.
Also add a reserve section for the secure code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/virt-dt.c
So far, only supporting the CPU_ON method.
Other functions can be added later.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 3 +
arch/arm/cpu/armv7/sunxi/psci.S | 162 ++
include/configs/sun7i.h | 6
Hi Albert,
On 2014-02-15 14:45, Albert ARIBAUD wrote:
On Sat, 15 Feb 2014 13:36:24 +, Marc Zyngier
marc.zyng...@arm.com
wrote:
PSCI is an ARM standard that provides a generic interface that
supervisory software can use to manage power in the following
situations:
There seems
Hi,
On 2014-02-25 13:38, Ezaul Zillmer wrote:
Hi Marc Zyngier
Where could obtain this repository with these alterations to be able
to
test
virtualization with KVM on my cubieboard2'm using Kernel 3.14.rc4
I appreciate if you help
You're looking at an older patch series. The new one can
Hi Siarhei,
On 03/08/14 03:36, Siarhei Siamashka wrote:
Unlike 9d195a546179bc732aba9eacccf0a9a3db591288, which had removed
the MIDR check against the white list of supported CPUs earlier,
now we introduce the black list of unsupported CPUs.
The current PSCI code is not compatible with the
On 06/08/14 10:49, Mark Rutland wrote:
On Wed, Aug 06, 2014 at 08:38:13AM +0100, Ian Campbell wrote:
On Mon, 2014-08-04 at 16:14 +0100, Marc Zyngier wrote:
My personal feeling is that booting in secure mode is always the wrong
thing to do.
FWIW I agree.
If you want to go down the road
On 07/08/14 02:54, Xiubo Li wrote:
The memory where loaded the smp_waitloop code section probablly
be corrupted by Linux Kernel, then the secondary cores will be
running the random code, leading booting the secondary cores
failed.
There is now similar reservation code in virt-dt.c. Probably
Hi Ian,
On 2014-05-01 19:40, Ian Campbell wrote:
This patch adds generic board, start of day and basic build system
support for
the Allwinner A20 (sun7i) processor. This code will not been compiled
until the
build is hooked up in a later patch. It has been split out to keep
the patches
On 2014-05-02 13:31, Ian Campbell wrote:
On Fri, 2014-05-02 at 10:45 +0100, Marc Zyngier wrote:
#define SUNXI_SRAM_D_BASE 0x01c0
+#define SUNXI_SRAM_B_BASE 0x01c0 /* 64 kiB (secure) */
Can we please fix these last two values which are obviously wrong
(at
least
On Fri, May 02 2014 at 9:13:08 pm BST, Jon Loeliger loeli...@gmail.com wrote:
On Sat, Apr 26, 2014 at 7:17 AM, Marc Zyngier marc.zyng...@arm.com wrote:
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
new file mode 100644
index 000..0b0d6a7
--- /dev/null
+++ b
On Fri, May 02 2014 at 9:30:05 pm BST, Jon Loeliger loeli...@gmail.com wrote:
Hi Jon,
I finally have all this working for me on an A9 system too!
Awesome! Ship it! ;-)
However, there were a few things that I had to change a bit.
For example, by CPUs will always come out of reset at 0x0
On Fri, May 02 2014 at 10:03:37 pm BST, Jon Loeliger loeli...@gmail.com wrote:
Mark,
In your nonsec_init code, you suggest this change:
+ mrc p15, 0, r0, c1, c1, 2
movwr1, #0x3fff
- movtr1, #0x0006
- mcr p15, 0, r1, c1, c1, 2 @ NSACR =
On Mon, May 05 2014 at 3:34:31 pm BST, Jon Loeliger loeli...@gmail.com wrote:
Mark,
Not sure on which patch of your series to base the following comment,
but thought it was worth bringing up for discussion nevertheless.
So, over in U-Boot ARMv7's arch/arm/cpu/armv7/start.S code, there
is
Hi Ian,
On 2014-05-07 20:24, Ian Campbell wrote:
On Sat, 2014-02-15 at 13:36 +, Marc Zyngier wrote:
@@ -32,5 +33,11 @@ int arch_fixup_fdt(void *blob)
size[bank] = bd-bi_dram[bank].size;
}
- return fdt_fixup_memory_banks(blob, start, size,
CONFIG_NR_DRAM_BANKS
Hi Liu,
On 30/05/14 03:25, tiger...@via-alliance.com wrote:
Hi, Marc:
I am studying ARMv8's u-boot code with FVP model.
In do_nonsec_virt_switch() function in bootm.c :
It will call smp_kick_all_cpus() function :
It seems it would set GICD_SGIR[24] = 1, forward the interrupt to all
CPU
On Tue, Jun 03 2014 at 3:16:19 am BST, tiger...@via-alliance.com
tiger...@via-alliance.com wrote:
Hi， Marc:
In short, if you're setting GICD_SGIR[24] to 1, you're sending SGI0 to
all CPUs but yourself. This seems to match the name of the function,
doesn't it?
I described my understanding based
On Tue, Jun 03 2014 at 10:41:51 am BST, tiger...@via-alliance.com
tiger...@via-alliance.com wrote:
Hi, Marc:
My understanding is that if you're using the Trusted Firmware, then you
have an implementation of PSCI, and that's what you must use to bring
the CPUs into u-boot. U-Boot will be running
On 08/06/14 08:57, Albert ARIBAUD wrote:
On Sun, 25 May 2014 16:08:44 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Marc,
On Sat, 26 Apr 2014 13:17:01 +0100, Marc Zyngier marc.zyng...@arm.com
wrote:
PSCI is an ARM standard that provides a generic interface that
supervisory
On 22/11/13 08:40, Ian Campbell wrote:
On Thu, 2013-11-21 at 15:04 +, Marc Zyngier wrote:
Hi Rob,
On 21/11/13 14:28, Rob Herring wrote:
On Thu, Nov 21, 2013 at 2:59 AM, Marc Zyngier marc.zyng...@arm.com wrote:
PSCI is an ARM standard that provides a generic interface that
supervisory
On 26/11/13 14:41, Andre Przywara wrote:
On 11/21/2013 09:59 AM, Marc Zyngier wrote:
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers
Hi Andre,
On 06/12/13 11:43, Andre Przywara wrote:
On 11/21/2013 09:59 AM, Marc Zyngier wrote:
PSCI is an ARM standard that provides a generic interface that
...
Thanks again for posting this, I like the idea of adding PSCI handlers
to u-boot for several platforms very much.
This patch
On 06/12/13 13:03, Andre Przywara wrote:
Yes, there is indeed this problem with the pen. Maybe one can use your
upcoming relocation code to move the pen to a more secure place (defined
per platform).
Yes, that's what I've done. Also rewritten some of it to be able to
execute solely in
at 12:12 +, Marc Zyngier wrote:
BTW: Yesterday my PSCI host patches for Xen have been committed, so Xen
should be able to use that feature just like the kernel does.
Excellent! I really need to sort these patches out and repost the whole
series...
I was hoping to give this a go on my cb2
In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.
Nothing is using it just yet.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/u-boot.lds | 30 ++
arch/arm/lib
not
subscribed to. Please keep me on Cc for any comment you may have.
Cheers,
M.
Marc Zyngier (13):
ARM: HYP/non-sec: fix alignment requirements for vectors
ARM: HYP/non-sec: move switch to non-sec to the last boot phase
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
ARM: non
Allow the switch to a second stage secure monitor just before
switching to non-secure.
This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...
Signed-off-by: Marc Zyngier marc.zyng
In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.
Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/include/asm/proc-armv
Having the switch to non-secure in the prep phase is causing
all kind of troubles, as that stage can be called multiple times.
Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm
Make sure the vectors are aligned on a 32 byte boundary, not
the code that deals with it...
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/Makefile | 4 ++
arch/arm/cpu/armv7/psci.S | 113
primitive.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 161 +++
arch/arm/cpu/armv7/virt-v7.c | 59 +-
arch/arm/include/asm/armv7.h | 10 ++-
arch/arm/include/asm/secure.h| 26 +++
arch/arm/lib
Move the B and D SRAM bank to their actual location (or at least
where the documentation pretends they are).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/include/asm/arch-sunxi/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm
CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/configs/sun7i.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include
So far, only supporting the CPU_ON method.
Other functions can be added later.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/sunxi/Makefile| 3 +
arch/arm/cpu/armv7/sunxi/psci.S | 124 +++
arch/arm/cpu/armv7/sunxi/u-boot
Commit b3a7f22b3e09 (ARM: vexpress: convert to common timer code)
converted the VE timer code to the generic framework, but hardcoded
the timer address of the A9 testchip.
Change it for the appropriate macro that works on both core tiles.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Generate the PSCI node in the device tree.
Also add a reserve section for the secure code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/virt-dt.c
On 07/12/13 21:03, Rob Herring wrote:
On Sat, Dec 7, 2013 at 5:11 AM, Marc Zyngier marc.zyng...@arm.com wrote:
Commit b3a7f22b3e09 (ARM: vexpress: convert to common timer code)
converted the VE timer code to the generic framework, but hardcoded
the timer address of the A9 testchip.
Change
On 09/12/13 10:51, Ian Campbell wrote:
On Sat, 2013-12-07 at 11:19 +, Marc Zyngier wrote:
The kernel now boots in HYP mode, finds its secondary CPU without any
SMP code present in the kernel, and runs KVM out of the box.
Hopefully, the Xen/ARM guys can do the same fairly easily.
Indeed
On 09/12/13 11:29, Hans de Goede wrote:
Hi,
On 12/09/2013 11:51 AM, Ian Campbell wrote:
On Sat, 2013-12-07 at 11:19 +, Marc Zyngier wrote:
The kernel now boots in HYP mode, finds its secondary CPU without any
SMP code present in the kernel, and runs KVM out of the box.
Hopefully
Cc: Marc Zyngier marc.zyng...@arm.com
---
This applies on top of Marc's ARMv7: add PSCI support to u-boot and allows
me
to chainload grub on a cubieboard2. (I don't think that has been applied
anywhere yet?)
Not yet, I'm still tinkering with it. See the current state at:
git
On 2014-10-11 12:27, Albert ARIBAUD wrote:
Hi Albert,
On Fri, 19 Sep 2014 18:04:14 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Marc,
On Thu, 18 Sep 2014 16:28:52 +0100, Marc Zyngier
marc.zyng...@arm.com
wrote:
On Thu, Sep 18 2014 at 10:12:17 AM, Albert ARIBAUD
albert.u.b
) support.
Signed-off-by: Hans de Goede hdego...@redhat.com
Looks good to me.
Acked-by: Marc Zyngier marc.zyng...@arm.com
M.
--
Jazz is not dead. It just smells funny.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman
On Wed, Oct 15 2014 at 11:25:10 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 15 Oct 2014 12:13:05 +0200
Hans de Goede hdego...@redhat.com wrote:
Older Linux kernels will not properly boot in hype mode, add support for a
bootm_boot_mode environment variable, which when set
On Wed, Oct 15 2014 at 11:25:43 AM, Albert ARIBAUD albert.u.b...@aribaud.net
wrote:
Hi Marc, Hans,
On Wed, 15 Oct 2014 11:18:28 +0100, Marc Zyngier marc.zyng...@arm.com
wrote:
On Wed, Oct 15 2014 at 11:13:05 AM, Hans de Goede hdego...@redhat.com
wrote:
Older Linux kernels
On Wed, Oct 15 2014 at 11:40:24 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 15 Oct 2014 11:31:44 +0100
Marc Zyngier marc.zyng...@arm.com wrote:
On Wed, Oct 15 2014 at 11:25:10 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 15 Oct 2014 12:13:05 +0200
On Wed, Oct 15 2014 at 03:05:24 PM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 15 Oct 2014 13:42:33 +0100
Marc Zyngier marc.zyng...@arm.com wrote:
On Wed, Oct 15 2014 at 11:40:24 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 15 Oct 2014 11:31:44 +0100
provided specifically for the
purpose.
So far no one is using this section.
Signed-off-by: Arnab Basu arnab.b...@freescale.com
Reviewed-by: Bhupesh Sharma bhupesh.sha...@freescale.com
Cc: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/config.mk|2 +-
arch/arm/cpu/armv8/u
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/Makefile | 4 ++
arch/arm/cpu/armv7/psci.S | 109
Allow the switch to a second stage secure monitor just before
switching to non-secure.
This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch
PSCI doesn't need any pen-related code, as it interacts directly
with the power controller.
Make these sections depend on CONFIG_ARMV7_PSCI not being set.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 2 ++
arch/arm/cpu/armv7/virt-v7.c | 2 ++
2
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu
So far, only supporting the CPU_ON method.
Other functions can be added later.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Makefile | 5 ++
arch/arm/cpu/armv7/sunxi/Makefile| 3 +
arch/arm/cpu/armv7/sunxi/config.mk | 6 +-
arch/arm/cpu
to. Please keep me on Cc for any comment you may have.
Cheers,
M.
Marc Zyngier (9):
ARM: HYP/non-sec: fix alignment requirements for vectors
ARM: HYP/non-sec: move switch to non-sec to the last boot phase
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
ARM: non-sec: reset
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...
Signed-off-by: Marc Zyngier marc.zyng
Having the switch to non-secure in the prep phase is causing
all kind of troubles, as that stage can be called multiple times.
Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm
CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/configs/sun7i.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include
Make sure the vectors are aligned on a 32 byte boundary, not
the code that deals with it...
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu
Hi Masahiro,
On 21/11/13 10:19, Masahiro Yamada wrote:
Hello Marc
+.align 5 @ Minimal alignment for vectors
+
/* the vector table for secure state and HYP mode */
_monitor_vectors:
.word 0 /* reset */
@@ -32,7 +34,6 @@ _monitor_vectors:
* to
Hi Rob,
On 21/11/13 14:28, Rob Herring wrote:
On Thu, Nov 21, 2013 at 2:59 AM, Marc Zyngier marc.zyng...@arm.com wrote:
PSCI is an ARM standard that provides a generic interface that
supervisory software can use to manage power in the following
situations:
- Core idle management
- CPU
On 22/11/13 03:58, Anup Patel wrote:
On 22 November 2013 07:24, Christoffer Dall christoffer.d...@linaro.org
wrote:
On 21 November 2013 07:04, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Rob,
On 21/11/13 14:28, Rob Herring wrote:
On Thu, Nov 21, 2013 at 2:59 AM, Marc Zyngier marc.zyng
On 22/11/13 01:54, Christoffer Dall wrote:
On 21 November 2013 07:04, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Rob,
On 21/11/13 14:28, Rob Herring wrote:
On Thu, Nov 21, 2013 at 2:59 AM, Marc Zyngier marc.zyng...@arm.com wrote:
PSCI is an ARM standard that provides a generic interface
On 22/11/13 01:51, Christoffer Dall wrote:
On 21 November 2013 00:59, Marc Zyngier marc.zyng...@arm.com wrote:
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7
On 16/04/14 15:45, Albert ARIBAUD wrote:
Hi Marc,
On Sat, 15 Feb 2014 13:36:24 +, Marc Zyngier
marc.zyngier-5wv7dgni...@public.gmane.org wrote:
PSCI is an ARM standard that provides a generic interface that
supervisory software can use to manage power in the following
situations
On Thu, Apr 17 2014 at 9:34:24 am BST, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Marc,
On Wed, 16 Apr 2014 17:09:07 +0100, Marc Zyngier marc.zyng...@arm.com
wrote:
On 16/04/14 15:45, Albert ARIBAUD wrote:
Hi Marc,
On Sat, 15 Feb 2014 13:36:24 +, Marc Zyngier
On Thu, Apr 17 2014 at 08:55:56 PM, Jon Loeliger loeli...@gmail.com wrote:
No, so far there hasn't been much discussion, and people seem happy with
it. I have a couple of fixes lined up, but nothing major.
So, I think PSCI 0.2 calls for function numbers in the 0x8400 range.
Seems like
On Thu, Apr 17 2014 at 09:01:07 PM, Jon Loeliger loeli...@gmail.com wrote:
[ Drat. I meant to send this to the U-Boot list, not just Albert. --jdl]
-- Forwarded message --
From: Jon Loeliger loeli...@gmail.com
Date: Thu, Apr 17, 2014 at 11:36 AM
Subject: Re: [U-Boot] [PATCH
In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.
Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/include/asm/proc-armv
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/lib/bootm-fdt.c | 2 +-
arch/arm/lib/bootm.c | 2 +-
common/image-fdt.c | 7 +--
include/common.h | 6 +++---
4 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/Makefile | 4 ++
arch/arm/cpu/armv7/psci.S | 102
Allow the switch to a second stage secure monitor just before
switching to non-secure.
This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch
In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.
Nothing is using it just yet.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/config.mk | 2 +-
arch/arm/cpu/u-boot.lds | 30
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...
Signed-off-by: Marc Zyngier marc.zyng
Having the switch to non-secure in the prep phase is causing
all kind of troubles, as that stage can be called multiple times.
Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm
primitive.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 161 +++
arch/arm/cpu/armv7/virt-v7.c | 59 +-
arch/arm/include/asm/armv7.h | 10 ++-
arch/arm/include/asm/secure.h| 26 +++
arch/arm/lib
allocation, timer macro).
- Rebased on mainline U-Boot (on top of 22a240c32c13).
From v1:
- Complete rewrite, now directly relocating the secure code withing
U-Boot, instead of having a separate psci blob.
Ma Haijun (1):
ARM: convert arch_fixup_memory_node to a generic FDT fixup function
Marc
Generate the PSCI node in the device tree.
Also add a reserve section for the secure code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/virt-dt.c
On 2014-04-26 15:24, Dennis Gilmore wrote:
On Sat, 26 Apr 2014 13:17:01 +0100
Marc Zyngier marc.zyng...@arm.com wrote:
PSCI is an ARM standard that provides a generic interface that
supervisory software can use to manage power in the following
situations:
- Core idle management
On 10/11/14 12:51, Jan Kiszka wrote:
Hi Marc,
what is the motivation to expose a PSCI 0.1 interface in U-boot, instead
of 0.2? Support for preexisting users of 0.1? The kernel seems to be
happy with both, and I'm now wondering if we should actually add the
legacy version to Jailhouse as
On 10/11/14 12:57, Jan Kiszka wrote:
Hi all,
I'm trying to get Marc's CPU hotplug-anabling patch [1] for sunxi
working on a B-Pi. After the first discussion it became clear that we
need something like flush_dcache_all in the PSCI monitor (I don't think
we need an icache flush, do we?). Does
On 10/11/14 13:25, Jan Kiszka wrote:
On 2014-11-10 14:08, Marc Zyngier wrote:
On 10/11/14 12:51, Jan Kiszka wrote:
Hi Marc,
what is the motivation to expose a PSCI 0.1 interface in U-boot, instead
of 0.2? Support for preexisting users of 0.1? The kernel seems to be
happy with both, and I'm
On Sun, Nov 16 2014 at 11:19:02 AM, Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-10-24 at 20:28 +0200, Hans de Goede wrote:
It is not used anywhere.
Might this be an oversight because sunxi is the only SoC with psci
support so far? Marc, was this added intentionally with a usecase in
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