Hi Daniel,
The spec for MIPS Unified Hosting Interface is available here:
http://prplfoundation.org/wiki/MIPS_documentation
As we have previously discussed, this is an ideal place to
define the handover of device tree data from bootloader to
kernel. Using a0 == -2 and defining which register(s)
James Hogan writes:
> On 26/02/15 12:37, Daniel Schwierzeck wrote:
> > 2015-02-26 11:17 GMT+01:00 Paul Burton :
> >> On Thu, Feb 19, 2015 at 01:50:23PM +0000, Matthew Fortune wrote:
> >>> Hi Daniel,
> >>>
> >>> The spec for MIPS Unified
Daniel Schwierzeck writes:
> When booting from ROM, early exceptions can't be handled
> properly. Instead of busy-looping give the developer the
> possibilty to examine the situation. Thus issue a SDBBP
> instruction to transfer control to hardware debugger if one
> is attached.
You could make th
Daniel Schwierzeck writes:
> will be simply exited. The SDBBP handler currently only
> prints the content of registers c0_depc and c0_debug. This
> could be extended in the future to handle semi-hosting
> according to the MIPS UHI specification.
Thanks for considering UHI in this. I worked on a
Daniel Schwierzeck writes:
> 2016-09-26 9:58 GMT+02:00 Matthew Fortune :
> > Daniel Schwierzeck writes:
> >> When booting from ROM, early exceptions can't be handled
> >> properly. Instead of busy-looping give the developer the
> >> possibilty to
Paul Burton writes:
> Some systems are configured such that multiple CPUs begin running from
> their reset vector following a system reset. If this occurs then U-Boot
> will be run on multiple CPUs simultaneously, which causes all sorts of
> issues as the multiple instances of U-Boot clobber each
Matthias Schiffer writes:
> >
> > I've disabled the builtin code and compared dissaemblies with and
> without your patch. Without your patch, gcc adds an additional store
> instruction before each cache instruction.
> >
> > E.g. for flush_dcache_range():
> >
> > 18: afa20008sw
Hi all,
I've been recently working on and promoting a common bare-metal semi-hosting
interface for the MIPS architecture. The main goal of this is to allow a
bare-metal MIPS application to run on the maximum number of simulation and
hardware platforms without (much/any) modification. The interface
Hi Daniel,
I'm looking for a bit of feedback on my query below. Unless there is a
major problem I'll start to organise an implementation for review.
Thanks,
Matthew
> -Original Message-
> From: Matthew Fortune
> Sent: 08 December 2014 12:43
> To: 'u-bo
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