create_tlb1_entry and create_tlb0_entry creates TLB entries with IPROT
bit set by default. Any TLB entries with IPROT = 1 can not be invalidated.
Add IPROT as input argument for TLB entry creation APIs.
Signed-off-by: Prabhakar Kushwaha
---
Based upon git://git.denx.de/u-boot.git branch master
On 06/04/2013 10:07 PM, Scott Wood wrote:
On 06/04/2013 11:36:17 AM, Scott Wood wrote:
On 06/04/2013 05:24:41 AM, Prabhakar Kushwaha wrote:
create_tlb1_entry and create_tlb0_entry creates TLB entries with IPROT
bit set by default. Any TLB entries with IPROT = 1 can not be
invalidated.
Add
init_tlbs() initialize all the TLB entries required for the system.
So disable DEBUG TLB entry before TLB entries initialization.
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/cpu/mpc85xx/cpu_init_early.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx
init_tlbs() initialize all the TLB entries required for the system.
So disable DEBUG TLB entry before TLB entries initialization.
Signed-off-by: Prabhakar Kushwaha
---
changes for v2: Fixed checkpatch warning.
arch/powerpc/cpu/mpc85xx/cpu_init_early.c |4
1 file changed, 4
On 06/22/2013 02:42 AM, Scott Wood wrote:
On 06/21/2013 04:05:37 PM, Fleming Andy-AFLEMING wrote:
On Jun 21, 2013, at 3:59 PM, Scott Wood wrote:
> On 06/21/2013 03:38:48 PM, Andy Fleming wrote:
>> On Thu, Jun 13, 2013 at 10:14:00AM +0530, Prabhakar Kushwaha wrote:
>> > init
On 06/24/2013 08:44 AM, Prabhakar Kushwaha wrote:
On 06/22/2013 02:42 AM, Scott Wood wrote:
On 06/21/2013 04:05:37 PM, Fleming Andy-AFLEMING wrote:
On Jun 21, 2013, at 3:59 PM, Scott Wood wrote:
> On 06/21/2013 03:38:48 PM, Andy Fleming wrote:
>> On Thu, Jun 13, 2013 at 10:14:0
On 06/24/2013 11:11 PM, Scott Wood wrote:
On 06/24/2013 01:17:11 AM, Prabhakar Kushwaha wrote:
On 06/24/2013 08:44 AM, Prabhakar Kushwaha wrote:
On 06/22/2013 02:42 AM, Scott Wood wrote:
On 06/21/2013 04:05:37 PM, Fleming Andy-AFLEMING wrote:
On Jun 21, 2013, at 3:59 PM, Scott Wood wrote
CONFIG_SPL_BUILD creates debug TLB entry, so disable it before init_tlbs.
CONFIG_SPL_INIT_MINIMAL never creates any debug TLB entry, so no need
of disable_tlb().
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/cpu/mpc85xx/cpu_init_early.c |3 ++-
1 file changed, 2 insertions(+), 1
On 06/25/2013 08:38 PM, Scott Wood wrote:
On 06/25/2013 12:03:56 AM, Prabhakar Kushwaha wrote:
CONFIG_SPL_BUILD creates debug TLB entry, so disable it before
init_tlbs.
CONFIG_SPL_INIT_MINIMAL never creates any debug TLB entry, so no need
of disable_tlb().
Signed-off-by: Prabhakar Kushwaha
On 06/27/2013 12:36 AM, Scott Wood wrote:
On 06/25/2013 11:09:04 PM, Prabhakar Kushwaha wrote:
On 06/25/2013 08:38 PM, Scott Wood wrote:
On 06/25/2013 12:03:56 AM, Prabhakar Kushwaha wrote:
CONFIG_SPL_BUILD creates debug TLB entry, so disable it before
init_tlbs.
CONFIG_SPL_INIT_MINIMAL
On 06/28/2013 09:49 PM, Scott Wood wrote:
On 06/28/2013 04:05:43 AM, Prabhakar Kushwaha wrote:
On 06/27/2013 12:36 AM, Scott Wood wrote:
On 06/25/2013 11:09:04 PM, Prabhakar Kushwaha wrote:
then it should be like this. slightly complex.
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) &&
!
CONFIG_SPL_BUILD creates debug TLB entry, so disable it before init_tlbs.
CONFIG_SPL_INIT_MINIMAL never creates any debug TLB entry, so no need
of disable_tlb().
Signed-off-by: Prabhakar Kushwaha
---
changes for v2: Removed checkpatch warning
changes for v3: Incorporated Scott's com
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: Prabhakar Kushwaha
Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start
accessing it.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Incorporated York's comments
- Update subject and description
board/freescale/t1040qds/t1040qds.c |5 +
include/configs/T1040
Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG.
Also add their details in README.
Signed-off-by: Prabhakar Kushwaha
---
Makefile|4 ++--
README |7 +++
include/configs/B4860QDS.h |4 ++--
include/configs
Thanks Wolfgang for reviewing this patch.
Please find my reply in-lined
On 1/13/2014 11:02 AM, Wolfgang Denk wrote:
Dear Prabhakar Kushwaha,
In message <1389587917-10324-1-git-send-email-prabha...@freescale.com> you
wrote:
Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG.
What
Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG.
Also add their details in README.
Signed-off-by: Prabhakar Kushwaha
---
changes for v2: Incorporated Wolfgang's comments
- Added more description in README
Makefile|4 ++--
R
On 1/10/2014 7:40 AM, Po Liu wrote:
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
On 1/14/2014 6:39 AM, Scott Wood wrote:
On Mon, 2014-01-13 at 11:58 +0530, Prabhakar Kushwaha wrote:
On 1/10/2014 7:40 AM, Po Liu wrote:
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 9de327b..6b43496 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.
So update acessor function with common IFC accessors to take care both
type of endianness.
Signed-off-by: Prabhakar Kushwaha
---
README
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.
So update acessor functions with common IFC acessor functions to take care
both type of endianness.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2
On 1/21/2014 12:04 PM, Wolfgang Denk wrote:
Dear Scott,
In message <20140121054228.de994382...@gemini.denx.de> I wrote:
I fear that more IP blocks will follow that have similar requirements,
and if we implemnt similar wrappers for each of them separately, we
will have a mess of hard to maintai
T1040 has only one SerDes block. so update the code accordingly.
Also, add support of SerDes Protocol 0x00, 0x06, 0x40, 0x69 0x85,
0xA7 and 0xAA
Signed-off-by: Arpit Goel
Signed-off-by: Poonam Aggrwal
Signed-off-by: Priyanka Jain
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/cpu
Signed-off-by: Priyanka Jain
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/include/asm/immap_85xx.h | 11 +
board/freescale/t1040qds/Makefile |1 +
board/freescale/t1040qds/eth.c| 492 +
board/freescale/t1040qds/t1040qds.c |1
Due to increased size of u-boot, FMAN ucode start address has been shifted
by 256KB causing a overlap with rootfs start address.
Update rootfs start address to reflect correct memory map.
Also fix minor typo in README
Signed-off-by: Prabhakar Kushwaha
---
board/freescale/t1040qds/README
Current print only display width of PCIe device. Add print to display
PCIe generation supported by the device.
Signed-off-by: Prabhakar Kushwaha
---
drivers/pci/fsl_pci_init.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci
d by other u-boot code
-Add CONFIG_SYS_CSPR2_EXT to make cpld accessible in u-boot
Signed-off-by: Prabhakar Kushwaha
---
include/configs/T1042RDB_PI.h | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_
d by other u-boot code
-Add CONFIG_SYS_CSPR2_EXT to make cpld accessible in u-boot
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2:
correct usb1 string for ;
include/configs/T1042RDB_PI.h | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/inclu
Signed-off-by: Poonam Aggrwal
Signed-off-by: Priyanka Jain
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2:
- Added missed sign off
arch/powerpc/include/asm/immap_85xx.h | 11 +
board/freescale/t1040qds/Makefile |1 +
board/freescale/t1040qds/eth.c| 492
Hi Andy,
Thanks for reviewing this patch.
Please find my reply in-lined
On Wednesday 25 April 2012 12:05 AM, Andy Fleming wrote:
On Thu, Mar 15, 2012 at 1:41 AM, Prabhakar Kushwaha
wrote:
- BSC9131 is integrated device that targets Femto base station market.
It combines Power
Hi,
Please find my reply in-lined.
On Wednesday 25 April 2012 12:58 AM, Andy Fleming wrote:
On Thu, Mar 15, 2012 at 1:44 AM, Prabhakar Kushwaha
wrote:
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
Hi,
On Wednesday 25 April 2012 02:50 AM, Andy Fleming wrote:
On Tue, Apr 24, 2012 at 4:10 PM, Scott Wood wrote:
On 04/24/2012 03:45 PM, Andy Fleming wrote:
On Mon, Mar 26, 2012 at 4:00 AM, Prabhakar Kushwaha
@@ -107,6 +107,7 @@
#define CONFIG_MAX_CPUS1
#define
Hi,
This patch has review-pending from a very long time.
I request the "mailing-list" to review this patch.
Regards,
Prabhakar
On Wednesday 15 February 2012 02:25 PM, Prabhakar Kushwaha wrote:
Built u-boot elf file does not contain any dwarf informations by default. This
info
stava
Signed-off-by: Prabhakar Kushwaha
---
Note: Name of PSC9131 has been changed to BSC9131 because of new nomenclature.
So please reject earlier patch:
"PSC9131/PSC9130/PSC9231 Processor Support Added"
http://patchwork.ozlabs.org/patch/141048/
-off-by: Rajan Srivastava
Signed-off-by: Poonam Aggrwal
Signed-off-by: Prabhakar Kushwaha
---
Note:
1) Name of PSC9131 has been changed to BSC9131 because of new
nomenclature.
So please reject earlier patch"powerpc/85xx:Add PSC9131 RDB Support"
This describes requirement of e500 and e500v2 processor to support external
debugger.
It also provide an insight of the configuration switch required and their
description.
Signed-off-by: Radu Lazarescu
Signed-off-by: Marius Grigoras
Signed-off-by: Prabhakar Kushwaha
---
Based upon git
: Marius Grigoras
Signed-off-by: Prabhakar Kushwaha
---
Based upon git://git.denx.de/u-boot.git branch master
Changes for v2:
- Avoid MSR_DE negation in arch_preboot
- Made MSR_DE set code independent of any #define
No change, Resending again
Tested on
- SoC having E500
-by: Radu Lazarescu
Signed-off-by: Marius Grigoras
Signed-off-by: Prabhakar Kushwaha
---
Based upon git://git.denx.de/u-boot.git branch master
Changes for v2:
- Put Temporary TLB creation under #define
Changes for v3:
- Removed unnecessary CONFIG_E500
- Updated
arius Grigoras
Signed-off-by: Prabhakar Kushwaha
---
Based upon git://git.denx.de/u-boot.git branch master
Changes for v2:
- Removed unnecessary CONFIG_E500
- Avoid TLB creation for NAND_SPL
Tested on
- SoC having E500 Family processor (P1010RDB, BSC9131RDB)
- SoC having E
lease refer doc/README.mpc85xx for more information
Signed-off-by: Radu Lazarescu
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/include/asm/config_mpc85xx.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/includ
Hi Scott,
On Wednesday 25 April 2012 08:20 PM, Scott Wood wrote:
On 04/24/2012 11:05 PM, Andy Fleming wrote:
On Tue, Apr 24, 2012 at 10:48 PM, Prabhakar Kushwaha
wrote:
Hi,
On Wednesday 25 April 2012 02:50 AM, Andy Fleming wrote:
On Tue, Apr 24, 2012 at 4:10 PM, Scott Wood
wrote
This describes requirement of e500 and e500v2 processor to support external
debugger.
It also provide an insight of the configuration switch required and their
description.
Signed-off-by: Radu Lazarescu
Signed-off-by: Marius Grigoras
Signed-off-by: Prabhakar Kushwaha
---
Based upon git
: Marius Grigoras
Signed-off-by: Prabhakar Kushwaha
---
Based upon git://git.denx.de/u-boot.git branch master
Changes for v2:
- Avoid MSR_DE negation in arch_preboot
- Made MSR_DE set code independent of any #define
No change, Resending again
Tested on
- SoC having E500
after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode
Signed-off-by: Radu Lazarescu
Signed-off-by: Marius Grigoras
Signed-off-by: Prabhakar Kushwaha
---
Based upon git://git.denx.de/u-boot.git branch master
Changes for v2:
- Put Temporary TLB creation under #define
arius Grigoras
Signed-off-by: Prabhakar Kushwaha
---
Based upon git://git.denx.de/u-boot.git branch master
Changes for v2:
- Removed unnecessary CONFIG_E500
- Avoid TLB creation for NAND_SPL
Changes for v3:
- Moved IVPR code out of CONFIG_NAND_SPL
- Placed this
During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.
Avoid updating these register.They will be programmed during NAND RAMBOOT.
Signed-off-by: Prabhakar Kushwaha
---
arch
ation
Signed-off-by: Radu Lazarescu
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/include/asm/config_mpc85xx.h | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 86
Hi Wolfgang,
This patch has been pending for a very long time. No review comments
has been provided.
Can you please review/accept this patch.
Regards,
Prabhakar
On 04/25/2012 09:41 AM, Prabhakar Kushwaha wrote:
Hi,
This patch has review-pending from a very long time.
I request the
Micron NOR flash present on T1040RDB and T1042RDB_PI do not support
write & read command running at same time.
CONFIG_SYS_FLASH_USE_BUFFER_WRITE reads NOR flash before performing write.
So, remove CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Signed-off-by: Prabhakar Kushwaha
---
include/con
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.
This support of CPLD includes
- files and register defintion
- Commands to swtich alternate bank and default bank
Signed-off-by: Prabhakar Kushwaha
---
board/freescale/t104xrdb/Makefile |1 +
board/freescale
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.
This support of CPLD includes
- files and register defintion
- Commands to swtich alternate bank and default bank
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2:
- Updated the cpld command
board
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.
This support of CPLD includes
- files and register defintion
- Commands to swtich alternate bank and default bank
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2:
- Updated the cpld command
Changes for v3
Signed-off-by: Prabhakar Kushwaha
---
Add support of 2 stage NAND boot loader in cornet platforms using SPL framework.
In current secenrio size of u-boot can become >=512KB. So This patch set will
be
helpful for those SoC which has less internal SRAM(512KB).
here, PBL initialise
SPL linker has fix location of bootpg and reset vector with respect to text
base.
It is not necessary to have fixed locations.
Avoid such hardcoding.
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |7 ++-
1 file changed, 6 insertions(+), 1 deletion
value.
Signed-off-by: Prabhakar Kushwaha
---
board/freescale/b4860qds/b4_pbi.cfg |3 +++
1 file changed, 3 insertions(+)
diff --git a/board/freescale/b4860qds/b4_pbi.cfg
b/board/freescale/b4860qds/b4_pbi.cfg
index 57b726e..05377ba 100644
--- a/board/freescale/b4860qds/b4_pbi.cfg
+++ b/board
-off-by: Prabhakar Kushwaha
---
README |3 +++
arch/powerpc/cpu/mpc85xx/start.S|2 ++
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 12
3 files changed, 17 insertions(+)
diff --git a/README b/README
index ff49260..3597a82 100644
--- a
It is not necessary for SPL to define all required LAW of the system.
Re-parse LAW table again during non SPL boot.
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/cpu/mpc8xxx/law.c |9 -
1 file changed, 9 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc
Objective of this target to have concatenate binary having
- SPL binary in PBL command format
- U-boot binary
Signed-off-by: Prabhakar Kushwaha
---
Makefile |9 +
README |4
2 files changed, 13 insertions(+)
diff --git a/Makefile b/Makefile
index 0281171
SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha
---
board/freescale/b4860qds/Makefile |9 ++-
board/freescale/b4860qds/ddr.c|6 +-
board/freescale/b4860qds/spl.c| 115
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha
---
drivers/mtd/nand/fsl_ifc_spl.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 2f82f7c..8a7a3a3
Signed-off-by: Prabhakar Kushwaha
---
Add support of 2 stage NAND boot loader in cornet platforms using SPL framework.
In current secenrio size of u-boot can become >=512KB. So This patch set will
be
helpful for those SoC which has less internal SRAM(512KB).
here, PBL initialise
SPL linker has fix location of bootpg and reset vector with respect to text
base.
It is not necessary to have fixed locations.
Avoid such hardcoding.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |7 ++-
1 file changed
-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
README |3 +++
arch/powerpc/cpu/mpc85xx/start.S|2 ++
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 12
3 files changed, 17 insertions(+)
diff --git a/README b/README
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.
So LAW_EN define outside of configs
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
It is not necessary for SPL to define all required LAW of the system.
Re-parse LAW table again during non SPL boot.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
arch/powerpc/cpu/mpc8xxx/law.c |9 -
1 file changed, 9 deletions(-)
diff --git a/arch
SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
board/freescale/b4860qds/Makefile |9 ++-
board/freescale/b4860qds/ddr.c|6 +-
board/freescale/b4860qds
Objective of this target to have concatenate binary having
- SPL binary in PBL command format
- U-boot binary
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Updated target
Makefile | 12
README |4
2 files changed, 16 insertions(+)
diff --git
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
drivers/mtd/nand/fsl_ifc_spl.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand
Hi Kumar,
On 3/6/2014 9:21 PM, Kumar Gala wrote:
On Mar 6, 2014, at 6:12 AM, Prabhakar Kushwaha wrote:
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Updated Makefile
Changes for v3:
- Updated B4860QDS.h config file to support B4420QDS NAND boot
- Fix B4860QDS_SPIFLASH B4420QDS_SPIFLASH build issue
Add support of 2 stage NAND boot loader in cornet platforms using SPL framework.
In
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ. It violates the IEEE specs.
So Slow MDC clock to comply IEEE specs
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Update commit message
board/freescale/b4860qds/b4_pbi.cfg |3 +++
1 file
-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
README |3 +++
arch/powerpc/cpu/mpc85xx/start.S|2 ++
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 12
3 files changed, 17 insertions
SPL linker has fix location of bootpg and reset vector with respect to text
base.
It is not necessary to have fixed locations.
Avoid such hardcoding.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
arch/powerpc/cpu/mpc85xx/u-boot
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
drivers/mtd/nand/fsl_ifc_spl.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand
Objective of this target to have concatenate binary having
- SPL binary in PBL command format
- U-boot binary
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Updated target
Changes for v3: Sending as it is
Makefile | 12
README |4
2 files
It is not necessary for SPL to define all required LAW of the system.
Re-parse LAW table again during non SPL boot.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
arch/powerpc/cpu/mpc8xxx/law.c |9 -
1 file changed, 9
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.
This support of CPLD includes
- files and register defintion
- Commands to swtich alternate bank and default bank
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2:
- Updated the cpld command
Changes for v3
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.
So LAW_EN define outside of configs
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3:
- Updated B4860QDS.h config file to support B4420QDS NAND boot
- Fix B4860QDS_SPIFLASH
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.
So LAW_EN define outside of configs
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Updated Makefile
Changes for v3:
- Updated B4860QDS.h config file to support B4420QDS NAND boot
- Fix B4860QDS_SPIFLASH B4420QDS_SPIFLASH build issue
Changes for v4:
- Updated Makefile with latest build format
Add support of 2 stage
-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is
README |3 +++
arch/powerpc/cpu/mpc85xx/start.S|2 ++
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 12
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.
So LAW_EN define outside of configs
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
It is not necessary for SPL to define all required LAW of the system.
Re-parse LAW table again during non SPL boot.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is
arch/powerpc/cpu/mpc8xxx/law.c |9
SPL linker has fix location of bootpg and reset vector with respect to text
base.
It is not necessary to have fixed locations.
Avoid such hardcoding.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is
Objective of this target to have concatenate binary having
- SPL binary in PBL command format
- U-boot binary
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Updated target
Changes for v3: Sending as it is
Changes for v4: Updated Makefile with latest build format
Makefile | 19
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is
drivers/mtd/nand/fsl_ifc_spl.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions
SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3:
- Updated B4860QDS.h config file to support B4420QDS NAND boot
- Fix B4860QDS_SPIFLASH
On 3/11/2014 11:46 AM, Yuantian Tang wrote:
-Original Message-
From: Sun York-R58495
Sent: Tuesday, March 11, 2014 1:45 AM
To: Tang Yuantian-B29983
Cc: u-boot@lists.denx.de; Li Yang-Leo-R58472; Jin Zhengxiong-R64188; Wood
Scott-B07421
Subject: Re: [PATCH 2/2 v2] mpc85xx/t104x: Add deep s
It is not necessary for bootpg to be present at text + 512KB.
With increase of u-boot size (768KB), bootpg section's address
cannot be fixed.
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds |8 +++-
arch/powerpc/cpu/mpc85xx/u-boot.lds |6
eSDHC host of T4x/B4x,T208x,T104x Soc has errata esdhc111. So add
macro definition to enable its workaround.
Signed-off-by: Haijun Zhang
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/include/asm/config_mpc85xx.h |4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc
U-boot binary size has been increased from 512KB to 768KB.
So update CONFIG_SYS_MONITOR_LEN to reflect the same.
Signed-off-by: Prabhakar Kushwaha
---
include/configs/B4860QDS.h |2 +-
include/configs/BSC9131RDB.h |2 +-
include/configs/BSC9132QDS.h |2 +-
include/configs
iable 'val' [-Wunused-variable]
fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable]
fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this
function [-Wuninitialized]
Signed-off-by: Prabhakar Kushwaha
---
drivers/mmc/fsl_e
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.
So LAW_EN define outside of configs
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/cpu/mpc85xx/start.S
Signed-off-by: Prabhakar Kushwaha
---
Add support of 2 stage boot loader in cornet platforms using SPL framework.
B4860QDS: NAND boot
T1040RDB: NAND, SD, SPI boot
T1042RDB_PI: NAND, SD, SPI boot
In current secenrio size of u-boot can become >=512KB. So This patch set will
be
helpful
GD(Global Data) structure has pointer to environment variable array.
but, it always point to default_environment assuming it is running from
final location.
So update GD pointer with env variable array during SPL boot.
Signed-off-by: Prabhakar Kushwaha
---
common/env_common.c |3 +++
1
SPL linker has fix location of bootpg and reset vector with respect to text
base.
It is not necessary to have fixed locations.
Avoid such hardcoding.
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |7 ++-
1 file changed, 6 insertions(+), 1 deletion
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha
---
drivers/mtd/nand/fsl_ifc_spl.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 2f82f7c..8a7a3a3
Before parsing LAW table i.e. init_law, boot loader should disable all
previous LAWs except DDR LAWs which has been created by previous
pre boot loader during DDR initialization.
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/cpu/mpc8xxx/law.c | 43
-off-by: Prabhakar Kushwaha
---
README |3 +++
arch/powerpc/cpu/mpc85xx/start.S|2 ++
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 12
3 files changed, 17 insertions(+)
diff --git a/README b/README
index 7cb7c4f..d8d5f60 100644
--- a
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