Re: [U-Boot] [PATCH v2 8/8] spi: cadence_qspi: Support specifying the sample edge used

Hi Phil, On Jum, 2016-11-25 at 14:38 +, Phil Edworthy wrote: > Whilst at it, move the code to read the "sram-size" property > into the other code that reads properties from the node, rather > than the SF subnode. > > Also change the code to use a bool for the bypass arg. > > Signed-off-by:

Re: [U-Boot] [PATCH v2 7/8] spi: cadence_qspi: Fix CS timings

Hi Phil, On Jum, 2016-11-25 at 14:38 +, Phil Edworthy wrote: > > The Cadence QSPI controller has specified overheads for the various > CS > times that are in addition to those programmed in to the Device Delay > register. The overheads are different for the delays. > > In addition, the

Re: [U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

On Jum, 2016-11-25 at 17:51 +0100, Marek Vasut wrote: > On 11/24/2016 06:35 AM, Vignesh R wrote: > > > > According to Section 11.15.4.9.2 Indirect Write Controller of K2G > > SoC > > TRM SPRUHY8D[1], the external master is only permitted to issue 32- > > bit > > data interface writes until the

Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

On Min, 2016-10-16 at 17:33 +0200, Marek Vasut wrote: > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > Separate the Clock Manager to support both GEN5 SoC and > > Stratix 10 SoC. > > > > Signed-off-by: Chin Liang See > > Cc: Marek Vasut > > Cc: Dinh

Re: [U-Boot] [PATCH v3 05/12] arm: socfpga: fpgamgr: Disable FPGA Manager for Stratix 10

On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote: > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > Disable the FPGA Manager for Stratix 10 SoC as we are not > > using this for SOCVP > If it's not used on SoCVP, then shouldn't this be disabled only for > SoCVP instead of S10 ? > We

Re: [U-Boot] [PATCH v3 01/12] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

On Min, 2016-10-16 at 17:31 +0200, Marek Vasut wrote: > On 10/13/2016 10:32 AM, Chin Liang See wrote: > > > > Add base address header file for Stratix10 SoC > > > > Signed-off-by: Chin Liang See > > Cc: Marek Vasut > > Cc: Dinh Nguyen

Re: [U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

On Sel, 2016-12-06 at 10:54 +0530, Vignesh R wrote: > > Hi, > > On Thursday 01 December 2016 09:41 AM, Vignesh R wrote: > [...] > > > > > > > > > > > > > > > > > > > > > > Data slave port does accept byte, half-word and word access, > > > > there > > > > are > > > > no data aborts. But

Re: [U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

On Tue, 2017-09-19 at 11:51 +0200, Marek Vasut wrote: > On 09/19/2017 11:22 AM, chin.liang@intel.com wrote: > > > > From: Chin Liang See > > > > Add the base address map for Statix10 SoC > > > > Signed-off-by: Chin Liang See > Add only

Re: [U-Boot] [PATCH 06/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

On Tue, 2017-09-26 at 17:46 -0500, Dinh Nguyen wrote: > On Tue, Sep 19, 2017 at 4:22 AM,   wrote: > > > > From: Chin Liang See > > > > Add misc support for Stratix SoC > Just because the file is call misc.c doesn't mean you can just keep > the

Re: [U-Boot] [PATCH 04/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

On Tue, 2017-09-26 at 17:08 -0500, Dinh Nguyen wrote: > On Tue, Sep 19, 2017 at 4:22 AM,   wrote: > > > > From: Chin Liang See > > > > Add Reset Manager driver support for Stratix SoC > > > > Signed-off-by: Chin Liang See

Re: [U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC

On Tue, 2017-09-26 at 17:04 -0500, Dinh Nguyen wrote: > On Tue, Sep 19, 2017 at 4:22 AM,   wrote: > > > > From: Chin Liang See > > > > Add Clock Manager driver support for Stratix SoC > > > > Signed-off-by: Chin Liang See

Re: [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC

On Tue, 2017-09-26 at 16:37 -0500, Dinh Nguyen wrote: > On Tue, Sep 19, 2017 at 4:22 AM,   wrote: > > > > From: Chin Liang See > > > > Device tree for Stratix10 SoC > > > > Signed-off-by: Chin Liang See > > --- > >  

Re: [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC

On Tue, 2017-09-26 at 16:34 -0500, Dinh Nguyen wrote: > On Tue, Sep 19, 2017 at 4:22 AM,   wrote: > > > > From: Chin Liang See > > > > Device tree for Stratix10 SoC > > > > Signed-off-by: Chin Liang See > > --- > >  

Re: [U-Boot] [PATCH] ARM: socfpga: Assure correct ACTLR configuration

On Tue, 2018-05-29 at 18:39 +0200, Marek Vasut wrote: > Make sure the ARM ACTLR register has correct configuration, otherwise > the Linux kernel refuses to boot. In particular, the "Write Full Line > of Zeroes" bit must be cleared. > > Signed-off-by: Marek Vasut > Cc: Chin Liang See > Cc: Dinh

Re: [U-Boot] [PATCH] ARM: socfpga: Pull DRAM size from DT

On Tue, 2018-05-29 at 18:37 +0200, Marek Vasut wrote: > Pull the DRAM size from DT instead of hardcoding it into U-Boot. > > Signed-off-by: Marek Vasut > Cc: Chin Liang See > Cc: Dinh Nguyen > --- >  arch/arm/mach-socfpga/misc.c | 4 +++- >  1 file changed, 3 insertions(+), 1 deletion(-) > >

Re: [U-Boot] [PATCH] ARM: socfpga: Make DRAM node available in SPL

On Tue, 2018-05-29 at 18:38 +0200, Marek Vasut wrote: > The SPL can also parse the DRAM configuration node to figure out the > memory layout, make sure it is available. > > Signed-off-by: Marek Vasut > Cc: Chin Liang See > Cc: Dinh Nguyen > --- >  arch/arm/dts/socfpga_arria10_socdk.dtsi | 1 +

Re: [U-Boot] [PATCH] ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10

On Tue, 2018-05-29 at 18:36 +0200, Marek Vasut wrote: > This function was never used in SPL and the default implementation of > dram_bank_mmu_setup() does the same thing. The only difference is the > part which configures OCRAM as cachable, which doesn't really work as > it covers more than the

Re: [U-Boot] [PATCH 0/5] Add DMA driver for DMA330 controller

On Thu, 2018-05-31 at 11:24 +0200, Marek Vasut wrote: > On 05/31/2018 10:08 AM, tien.fong.c...@intel.com wrote: > > > > From: Tien Fong Chee > > > > This patchset contains dm driver for DMA330 controller. > > > > This series is working on top of u-boot-socfpga.git - > >  

Re: [U-Boot] [PATCH] ARM: socfpga: Assure correct ACTLR configuration

On Sat, 2018-06-23 at 06:23 +0200, Marek Vasut wrote: > On 06/23/2018 05:55 AM, Marek Vasut wrote: > > > > On 06/06/2018 08:47 PM, Marek Vasut wrote: > > > > > > On 05/31/2018 12:00 PM, Marek Vasut wrote: > > > > > > > > On 05/31/2018 11:

Re: [U-Boot] [PATCH 2/2] arm: socfpga: cyclone5: Ensure spi-flash in the compatible string

On Wed, 2018-02-21 at 10:34 +0100, Simon Goldschmidt wrote: > On 21.02.2018 08:40, chin.liang@intel.com wrote: > > > > From: Chin Liang See > > > > Ensure "spi-flash" is added into compatible string when there is > > NOR flash being instantiated in DTS. Discovered

Re: [U-Boot] [PATCH 1/2] arm: socfpga: cyclone5: Enable Macronix flash support

On Wed, 2018-02-21 at 20:23 +0100, Marek Vasut wrote: > On 02/21/2018 08:39 AM, chin.liang@intel.com wrote: > > > > From: Chin Liang See > > > > Enable Macronix flash support for Cyclone5 SoC > Do these boards actually have a macronix flash ? Most of the ones I >

Re: [U-Boot] [PATCH 1/2] arm: socfpga: cyclone5: Enable Macronix flash support

On Thu, 2018-02-22 at 11:45 +0100, Marek Vasut wrote: > On 02/22/2018 07:29 AM, See, Chin Liang wrote: > > > > On Wed, 2018-02-21 at 20:23 +0100, Marek Vasut wrote: > > > > > > On 02/21/2018 08:39 AM, chin.liang@intel.com wrote: > > > > >

Re: [U-Boot] [PATCH] arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast

On Thu, 2018-03-01 at 17:17 +0100, Marek Vasut wrote: > On 02/28/2018 06:12 AM, chin.liang@intel.com wrote: > > > > From: Chin Liang See > > > > Enabling cache and TLB maintenance broadcast through ACTLR as > > required > > by Linux. > This needs far more

Re: [U-Boot] [PATCH 3/5] tools: socfpga: Stop using global struct socfpga_image

On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote: > The structure is passed around correctly, create local instances > where necessary and zap the global struct socfpga_image instance. > > Signed-off-by: Marek Vasut > Cc: Dinh Nguyen > Cc: Chin Liang See

Re: [U-Boot] [PATCH 5/5] spl: socfpga: Generate Arria10 SFP header V1

On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote: > Generate SoCFPGA boot header version 1 instead of version 0 for > Arria10. > > Signed-off-by: Marek Vasut > Cc: Dinh Nguyen > Cc: Chin Liang See > --- >  scripts/Makefile.spl |

Re: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for Arria10

Hi Marek, On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote: > The Arria10 uses slightly different boot image header than the Gen5 > SoCs, > in particular the header itself contains an offset from the start of > the > header to which the Arria10 jumps. This offset must not be negative, > yet >

Re: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for Arria10

On Tue, 2018-04-17 at 11:01 +0200, Marek Vasut wrote: > On 04/17/2018 10:52 AM, See, Chin Liang wrote: > > > > On Tue, 2018-04-17 at 10:46 +0200, Marek Vasut wrote: > > > > > > On 04/17/2018 10:40 AM, See, Chin Liang wrote: > > > > > > > &g

Re: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for Arria10

On Tue, 2018-04-17 at 10:46 +0200, Marek Vasut wrote: > On 04/17/2018 10:40 AM, See, Chin Liang wrote: > > > > Hi Marek, > > > > On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote: > > > > > > The Arria10 uses slightly different boo

Re: [U-Boot] [PATCH 2/5] image: socfpga: Add SFP image version 1 definition

On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote: > Add support for the SoCFPGA header v1, which is used on Arria 10. > The layout of the v0 and v1 header is similar, yet there are a few > differences which make it incompatible with previous v0 header, so > add a new entry. > > Signed-off-by:

Re: [U-Boot] [PATCH v1 05/16] arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote: > On 04/19/2018 11:50 AM, Ley Foon Tan wrote: > > > > Add CONFIG_SYS_L2_PL310 conditional build. > Why ? > In ARM64, L2 cache controller is accessed through processor registers. Hence we shall make this conditional in order this file can be

Re: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for Arria10

On Tue, 2018-04-17 at 11:28 +0200, Marek Vasut wrote: > On 04/17/2018 11:11 AM, See, Chin Liang wrote: > > > > On Tue, 2018-04-17 at 11:01 +0200, Marek Vasut wrote: > > > > > > On 04/17/2018 10:52 AM, See, Chin Liang wrote: > > > > > > > >

Re: [U-Boot] [PATCH v1 13/16] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

On Thu, 2018-04-19 at 04:59 +0200, Marek Vasut wrote: > On 04/19/2018 11:50 AM, Ley Foon Tan wrote: > > > > Add timer support for Stratix SoC > Is this really custom timer or is that some armv8 thing you're adding > here ? Don't we already have a generic implementation for that ? If > not, >

Re: [U-Boot] [PATCH v2 2/2] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED

On Tue, 2019-06-04 at 07:13 +0200, Simon Goldschmidt wrote: > On Tue, Jun 4, 2019 at 1:57 AM Dalon Westergreen > wrote: > > > > > > From: Dalon Westergreen > > > > CONFIG_OF_EMBED was primarily enabled to support the stratix10 > > spl hex file requirements.  Since this option now produces a >

Re: [U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()

On Mon, 2019-04-29 at 10:34 +0200, Marek Vasut wrote: > On 4/26/19 8:39 AM, Simon Goldschmidt wrote: > > > > On Tue, Apr 23, 2019 at 6:14 PM Marek Vasut wrote: > > > > > > > > > The usage of socfpga_sdram_apply_static_cfg() seems rather > > > dubious and > > > is confirmed to lead to a rare