[U-Boot] [PATCH] powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen node

From: Tang Yuantian yuantian.t...@freescale.com For T4/B4, the clockgen node compatible string is updated to version 2. Add clock-frequency setting for this new version. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/powerpc/cpu/mpc85xx/fdt.c |2 ++ 1 files changed, 2

[U-Boot] [PATCH] powerpc/mpc85xx: Fix the I2C bus speed error on p1022

From: Tang Yuantian yuantian.t...@freescale.com The source clock frequency of I2C bus on p1022 is the platform(CCB) clock, not CCB/2. The wrong source clock frequency leads to wrong I2C bus speed setting. so, fixed it. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- fix bug:

[U-Boot] [PATCH v3] powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen node

From: Tang Yuantian yuantian.t...@freescale.com For T4/B4, the clockgen node compatible string is updated to version 2.0. Add clock-frequency setting for this new version. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- v3: - update the compatible string from *-2 to *-2.0

[U-Boot] [PATCH 1/2 v2] mpc85xx: Add support for the supplement configuration unit register

From: Tang Yuantian yuantian.t...@freescale.com The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in

[U-Boot] [PATCH 2/2 v2] mpc85xx/t104x: Add deep sleep framework support

From: Tang Yuantian yuantian.t...@freescale.com When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before.

[U-Boot] [PATCH 1/2] powerpc/mpc85xx: Make boot flag effective

From: Tang Yuantian yuantian.t...@freescale.com bootflag as a parameter is passed to board_init_f(). But it is not actually used in this function. Make it effective by assigned it to gd-flags. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/powerpc/lib/board.c | 2 ++ 1 file

[U-Boot] [PATCH 2/2] powerpc/t104xrdb: support deep sleep in SPI/SD boot

From: Tang Yuantian yuantian.t...@freescale.com Add deep sleep support in SPI/SD boot. The destination address second stage uboot image is loaded to is changed because currently this address will be used by kernel which means we can't reserve it for resume. Entry point to kernel is still placed

[U-Boot] [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms

From: Tang Yuantian yuantian.t...@freescale.com These patches depend on the following patches: https://patchwork.ozlabs.org/patch/389949/ https://patchwork.ozlabs.org/patch/389950/ https://patchwork.ozlabs.org/patch/389951/ https://patchwork.ozlabs.org/patch/389952/ Tang Yuantian (4): Add deep

[U-Boot] [PATCH 3/4] arm: ls102xa: Fixed a register definition error

From: Tang Yuantian yuantian.t...@freescale.com There are 8 SCFG_SPARECR registers in SCFG memory block, not one. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[U-Boot] [PATCH 2/4] ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation

From: Tang Yuantian yuantian.t...@freescale.com Defining variable gic_dist_addr as a globe one prevents function armv7_init_nonsec() from being used before relocation which is the case in the deep sleep resume process on Freescale QorIQ SoC platforms. This patch removes this limitation by adding

[U-Boot] [PATCH 4/4] arm: ls1021qds: Add deep sleep support

From: Tang Yuantian yuantian.t...@freescale.com Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- board/freescale/ls1021aqds/ddr.c| 7 board/freescale/ls1021aqds/ls1021aqds.c | 60 +

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

From: Tang Yuantian yuantian.t...@freescale.com When Freescale QorIQ SoCs wake up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves

[U-Boot] [PATCH 1/4] Add deep sleep framework support for Freescale QorIQ platforms

From: Tang Yuantian yuantian.t...@freescale.com When Freescale QorIQ SoCs wake up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves

[U-Boot] [PATCH 3/4] arm: ls102xa: Fixed a register definition error

From: Tang Yuantian yuantian.t...@freescale.com There are 8 SCFG_SPARECR registers in SCFG memory block, not one. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[U-Boot] [PATCH 4/4] arm: ls1021qds: Add deep sleep support

From: Tang Yuantian yuantian.t...@freescale.com Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- board/freescale/ls1021aqds/ddr.c| 7 board/freescale/ls1021aqds/ls1021aqds.c | 60 +

[U-Boot] [PATCH 2/4] ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation

From: Tang Yuantian yuantian.t...@freescale.com Defining variable gic_dist_addr as a globe one prevents function armv7_init_nonsec() from being used before relocation which is the case in the deep sleep resume process on Freescale QorIQ SoC platforms. This patch removes this limitation by adding

[U-Boot] [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms

From: Tang Yuantian yuantian.t...@freescale.com These patches depend on the following patches: https://patchwork.ozlabs.org/patch/389949/ https://patchwork.ozlabs.org/patch/389950/ https://patchwork.ozlabs.org/patch/389951/ https://patchwork.ozlabs.org/patch/389952/ Tang Yuantian (4): Add deep

[U-Boot] [PATCH] arm: ls102xa: fixed a bus frequency setting error

From: Tang Yuantian yuantian.t...@freescale.com The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1

[U-Boot] [PATCH v2] mpc85xx: Fix the offset of register address error

From: Tang Yuantian yuantian.t...@freescale.com The offset of register address within GPIO module is just CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080, P5020, P5040, T4240, B4860. Signed-off-by: Tang Yuantian

[U-Boot] [PATCH] mpc85xx/p1022ds: convert to generic board

From: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- include/configs/P1022DS.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 54e2569..de0613f 100644 ---

[U-Boot] [PATCH 1/3] powerpc: add deep sleep support for generic board

From: Tang Yuantian yuantian.t...@freescale.com Deep sleep for generic board is not supported on PowerPC. This patch make deep sleep work for both non-generic board and generic board on PowerPC platforms. For ARM-based QorIQ platforms, deep sleep has been already supported. Signed-off-by: Tang

[U-Boot] [PATCH] powerpc/t104xrdb: add deep sleep support

From: Tang Yuantian yuantian.t...@freescale.com Added deep sleep support on T104xRDB platforms. Support both SD/SPI boot and NOR boot. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- board/freescale/t104xrdb/spl.c | 41 +++--

[U-Boot] [PATCH 3/3] powerpc/t102xrdb: add deep sleep support

From: Tang Yuantian yuantian.t...@freescale.com Added deep sleep support on T102xRDB platforms. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- board/freescale/t102xrdb/t102xrdb.c | 66 + include/configs/T102xRDB.h | 2 +- 2 files

[U-Boot] [PATCH] fsl/sleep: updated the deep sleep framework for QorIQ platforms

From: Tang Yuantian yuantian.t...@freescale.com With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to

[U-Boot] [PATCH] mpc85xx/t104xrdb: convert deep sleep to generic board interface

From: Tang Yuantian yuantian.t...@freescale.com A new interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- board/freescale/t104xrdb/ddr.c | 19 +++

[U-Boot] [PATCH] ahci: Fix a wrong parameter pass

From: Tang Yuantian yuantian.t...@freescale.com In stead of user_buffer_size, transfer_size should be used to pass to ahci_device_data_io(). transfer_size is the length that we want the low level function to transfer each time. If we use user_buffer_size which is the totally data length as

[U-Boot] [PATCH] fsl/deepsleep: avoid the DDR restore from being optimized out

From: Tang Yuantian yuantian.t...@freescale.com Function dp_ddr_restore is to restore the first 128-byte space of DDR. However those codes may be optimized out by compiler since the destination address is at 0x0. In order to avoid compiler optimization, we restore the space from high address,

[U-Boot] [PATCH] fsl/sata: Replace sprintf() with snprintf()

From: Tang Yuantian yuantian.t...@freescale.com Function 'sprintf' does not check buffer boundaries but outputs to the buffer of fixed size which could cause buffer overflow. Use a safer function to replace it. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com ---

[U-Boot] [PATCH] fsl/sata: Replace sprintf() with snprintf()

From: Tang Yuantian yuantian.t...@freescale.com Function 'sprintf' does not check buffer boundaries but outputs to the buffer of fixed size which could potentially cause buffer overflow. Use a safer function to replace it. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com ---

[U-Boot] [PATCH] ls1021atwr: added deep sleep support in uboot

From: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++ board/freescale/ls1021atwr/ls1021atwr.c | 68 ++- include/configs/ls1021atwr.h

[U-Boot] [PATCH] ahci: Fix compiling warnings under 64bit platforms

From: Tang Yuantian yuantian.t...@freescale.com When compling under 64bit platforms, there are lots of warnings, like: drivers/block/ahci.c:114:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;

[U-Boot] [PATCH v2] ahci: Fix compiling warnings under 64bit platforms

From: Tang Yuantian yuantian.t...@freescale.com When compling under 64bit platforms, there are lots of warnings, like: drivers/block/ahci.c:114:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;

[U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board

From: Tang Yuantian yuantian.t...@freescale.com Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian

[U-Boot] [PATCH v2] arm/ls2085a: Add sata support on qds and rdb board

From: Tang Yuantian yuantian.t...@freescale.com Freescale ARM-based Layerscape LS2085A contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2085aqds and ls2085ardb boards. Signed-off-by: Tang Yuantian

[U-Boot] [PATCH] layerscape: sata: Add layerscape sata support

From: Tang Yuantian yuantian.t...@freescale.com Freescale ARM-based Layerscape SoCs contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds some basic SATA APIs which would be called by specific board. Signed-off-by: Tang

[U-Boot] [PATCH v3] ahci: Fix compiling warnings under 64bit platforms

From: Tang Yuantian yuantian.t...@freescale.com When compling under 64bit platforms, there are lots of warnings, like: drivers/block/ahci.c:114:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] u8 *port_mmio = (u8 *)probe_ent-port[port].port_mmio;

[U-Boot] [PATCH v6] arm: Add sata support on Layerscape ARMv8 board

From: Tang Yuantian Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang

[U-Boot] [PATCH v5] arm: Add sata support on Layerscape ARMv8 board

From: Tang Yuantian Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang

[U-Boot] [PATCH] arm: ls1021a: Adjust sata register default values

From: Tang Yuantian Updated the default sata register values to enhance the performance and stability. Signed-off-by: Tang Yuantian --- arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 10 +- 1 file changed, 5 insertions(+), 5

[U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board

From: Tang Yuantian Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang

[U-Boot] [PATCH] ahci: flush dcache before issuing command

From: Tang Yuantian Ensure data the following sata command used is flushed out of dcache and written to physical memory or timeout error may happen. Signed-off-by: Tang Yuantian --- drivers/block/ahci.c | 1 + 1 file changed, 1 insertion(+) diff

[U-Boot] [PATCH 2/2] armv8: fsl-lsch2: enable snoopable sata read and write

From: Tang Yuantian By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA

[U-Boot] [PATCH 1/2] armv8: fsl-lsch2: adjust sata parameter

From: Tang Yuantian The default values for Port Phy2Cfg register and Port Phy3Cfg register are better, no need to overwrite them. Signed-off-by: Tang Yuantian --- arch/arm/cpu/armv8/fsl-layerscape/soc.c| 2 --

[U-Boot] [PATCH v2] armv8: fsl-lsch2: add workaround for erratum A-010635

From: Tang Yuantian Read DMA operations causes CRC error on armv8 chassis 2 platforms due to the erratum A-010635. In order to support sata on these platforms, ECC needs to be disabled. Signed-off-by: Tang Yuantian --- v2: - refine the commit

[U-Boot] [PATCH v2] armv8: fsl-lsch2: add workaround for erratum A-010635

From: Tang Yuantian Read DMA operations causes CRC error on armv8 chassis 2 platforms due to the erratum A-010635. In order to support sata on these platforms, ECC needs to be disabled. Signed-off-by: Tang Yuantian --- v2: - refine the commit

[U-Boot] [PATCH] armv8: fsl-lsch2: disable ECC for sata on armv8 chassis 2 platforms

From: Tang Yuantian The Read DMA operations get early termination indication from the controller. This issue is observed as CRC error in the status registers. The issue is due to address collision at address 0 in the dual port memory. The read is a dummy read to flush out

[U-Boot] [PATCH 2/2] armv8: ls1046a: enable usb in defconfig

From: Tang Yuantian Signed-off-by: Tang Yuantian --- configs/ls1046aqds_defconfig | 2 ++ configs/ls1046aqds_lpuart_defconfig | 2 ++ configs/ls1046aqds_nand_defconfig| 2 ++ configs/ls1046aqds_qspi_defconfig| 2 ++

[U-Boot] [PATCH v2] armv8: ls1046aqds: added usb feature support

From: Tang Yuantian The LS1046AQDS processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device,

[U-Boot] [PATCH 1/2] armv8: ls1046a: added usb nodes in dts

From: Tang Yuantian The LS1046A processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which

[U-Boot] [PATCH] sata: fix sata command not being executed bug

From: Tang Yuantian Variable sata_curr_device is used to indicate if there is a available sata disk on board. Previously, sata_curr_device is set in sata_initialize(). Now, sata_initialize() is separated from other sata commands. Accordingly, sata_curr_device is removed

[U-Boot] [PATCH v2] sata: Fixes:d97dc8a0(Separate the non-command code into its own file)

From: Tang Yuantian Commit d97dc8a0 separated the non-command code into its own file which caused variable sata_curr_device can not be set to a correct value. Before commit d97dc8a0, variable sata_curr_device can be set correctly in sata_initialize(). After commit

[U-Boot] [PATCH] sata: fix sata command can not being executed bug

From: Tang Yuantian Commit d97dc8a0 separated the non-command code into its own file which caused variable sata_curr_device can not be set to a correct value. Before commit d97dc8a0, variable sata_curr_device can be set correctly in sata_initialize(). After commit

[U-Boot] [PATCH] armv8: fsl-lsch3: enable snoopable sata read and write

From: Tang Yuantian By default the SATA IP on the ls208Xa SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. Signed-off-by: Tang Yuantian --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 ++

[U-Boot] [PATCH 1/2] armv8: ls1012: added usb nodes in dts

From: Tang Yuantian The LS1012A processor has two integrated USB controllers. One is USB2.0 controller, the other is USB3.0 controller that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. Signed-off-by: Tang Yuantian

[U-Boot] [PATCH 2/2] armv8: ls1012: Enable CONFIG_DM_USB in defconfigs

From: Tang Yuantian Enables driver model flag CONFIG_DM_USB for LS1012A platform in defconfigs. Signed-off-by: Tang Yuantian --- configs/ls1012afrdm_qspi_defconfig | 1 + configs/ls1012aqds_qspi_defconfig | 1 + configs/ls1012ardb_qspi_defconfig

[U-Boot] [PATCH 1/2] armv8: ls1046a: added usb feature support

From: Tang Yuantian The LS1046A processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which

[U-Boot] [PATCH 2/2] armv8: ls1046a: enable usb in defconfig

From: Tang Yuantian Signed-off-by: Tang Yuantian --- configs/ls1046aqds_defconfig | 6 ++ configs/ls1046aqds_lpuart_defconfig | 6 ++ configs/ls1046aqds_nand_defconfig| 6 ++ configs/ls1046aqds_qspi_defconfig

[U-Boot] [PATCH] armv8: ls1046aqds: added usb feature support

From: Tang Yuantian The LS1046AQDS processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device,