From: Shaohui Xie
Also, remove workaround of rev1.0.
Signed-off-by: Shaohui Xie
---
board/freescale/t4qds/t4_pbi.cfg | 17 +++--
board/freescale/t4qds/t4_rcw.cfg | 6 +++---
2 files changed, 6 insertions(+), 17 deletions(-)
diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/fr
From: Shaohui Xie
Also, remove workaround of rev1.0.
Signed-off-by: Shaohui Xie
---
board/freescale/t4qds/t4_pbi.cfg | 14 --
board/freescale/t4qds/t4_rcw.cfg | 4 ++--
2 files changed, 2 insertions(+), 16 deletions(-)
diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freesca
From: Shaohui Xie
Also, remove workaround of rev1.0.
Signed-off-by: Shaohui Xie
---
board/freescale/t4qds/t4_pbi.cfg | 14 --
board/freescale/t4qds/t4_rcw.cfg | 6 +++---
2 files changed, 3 insertions(+), 17 deletions(-)
diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/frees
From: Shaohui Xie
XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.
So, for XFI usage, there are two scenarios, on
From: Shaohui Xie
XFI ports on t2080qds can work with fiber cable and direct attach
cable(copper). We use hwconfig to define cable type for XFI, and fixup
dtb based on the cable type.
For copper cable, set below env in hwconfig:
fsl_10gkr_copper:<10g_mac_name>
the <10g_mac_name> can be fm1_10g
From: Shaohui Xie
1000BASE-KX(1GKX) uses same SGMII interface but the serdes lane run in
1GKX mode. By default, the lane runs in SGMII mode, when a MAC runs in
1GKX mode, the corresponding lane mode needs to be set accordingly.
DTB needs the fixup for kernel to do proper initialization.
hwconfig
From: Shaohui Xie
XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.
So, for XFI usage, there are two scenarios, on
From: Shaohui Xie
XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.
So, for XFI usage, there are two scenarios, on
From: Shaohui Xie
1. use Payload length check disable when enable MAC;
2. add XGMII support for setting MAC interface mode;
3. only enable auto negotiation for Non-XGMII mode;
4. return 0x if clause 22 is used to read 10G phy_id;
Signed-off-by: Shaohui Xie
Signed-off-by: Roy Zang
---
arch
From: Shaohui Xie
NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some
platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure
on XAUI PHY, so set this bit definitely to align with the RM.
Signed-off-by: Shaohui Xie
---
arch/powerpc/include/asm/fsl_memac.h |
From: Shaohui Xie
1. board/freescale/t4qds/t4_rcw.cfg
1.8GHz support is requested as default frequency, so update the rcw.
2. remove un-used configs
configs/T4160QDS_SPIFLASH_defconfig
configs/T4240QDS_SPIFLASH_defconfig
SPI boot is not available on T4QDS, so the configs should be removed.
3. b
From: Shaohui Xie
cpld reset altbank should always reset to bank4 no matter what current
bank is.
Signed-off-by: Shaohui Xie
---
board/freescale/t4rdb/cpld.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
i
From: Shaohui Xie
1000BASE-KX(1G-KX) uses SGMII protocol but the serdes lane runs in 1G-KX
mode. By default, the lane runs in SGMII mode, when a MAC uses a lane
in 1G-KX mode, corresponding bit in PCCR1 for the lane needs to be set,
and needs to fixup dtb accordingly for kernel to do proper initi
From: Shaohui Xie
Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.
Signed-off-by: Shaohui Xie
---
board/freescale/b4860qds/b4_pbi.cfg | 27 +++
board/freescal
From: Shaohui Xie
On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.
Signed-off-by: Shaohui Xie
---
based on 'next' of git://git.denx.de/u-boot-mpc85xx.git.
include/configs/B4860QDS.h | 2 +-
in
From: Shaohui Xie
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.
Signed-off-by: Shaohui Xie
---
arch/powerpc/include/asm/immap_85xx.h | 6 ++
board/freescale/t4qds/t4240qds.c | 10 ++
2 files changed, 12 inse
From: Shaohui Xie
Signed-off-by: Shaohui Xie
---
include/configs/P4080DS.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index b0cd7d5..2f89008 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -17,6 +17,1
From: Shaohui Xie
fixed-link is used in kernel for PHY-less MAC, so introduce this
structure that U-boot can use it to fixup dtb dynamically.
Signed-off-by: Shaohui Xie
---
include/phy.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/phy.h b/include/phy.h
index f0f522a..f8
From: Shaohui Xie
The VSC8514 works in QSGMII interface. Its register set and features
are similar to VSC8574 which in QSGMII mode.
Signed-off-by: Shaohui Xie
---
drivers/net/phy/vitesse.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/
From: Shaohui Xie
A new valid setting case added for fman1, it uses platform frequency.
Signed-off-by: Shaohui Xie
---
based on patch: http://patchwork.ozlabs.org/patch/294663/
arch/powerpc/cpu/mpc85xx/speed.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/spe
From: Dave Liu
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.
Signed-off-by: Dave Liu
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/m
From: Shaohui Xie
Signed-off-by: Shaohui Xie
---
boards.cfg | 1 +
1 file changed, 1 insertion(+)
diff --git a/boards.cfg b/boards.cfg
index 2128996..302ac56 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -966,6 +966,7 @@ Active powerpc mpc85xx- freescale
t4qds
Acti
From: Shaohui Xie
The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1.
Signed-off-by: Shaohui Xie
---
board/freescale/b4860qds/b4_rcw.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/b4860qds/b4_rcw.cfg
b/board/freescale/b4860qds/b4_rcw.
From: Shaohui Xie
Default configuration has been changed, the most important one is DDR
ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to
change from 24x to 12x to keep the DDR frequency. There are also some
other optimise to align with default configuration.
Signed-off
From: Shaohui Xie
Previous process of compiling a PBL boot image is:
1: make
2: make u-boot.pbl
for example:
make T4240QDS_SDCARD_config
make u-boot.pbl
Now the process is:
1: make
for example:
make T4240QDS_SDCARD
Also, updated README.pblimage.
Signed-off-by: Shaohui Xie
---
Makefile
From: Shaohui Xie
There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it
will fall into case PHY_INTERFACE_MODE_RGMII.
Signed-off-by: Shaohui Xie
---
board/freescale/t104xrdb/eth.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/freescale/t104xrdb/eth.c b/board/frees
From: Shaohui Xie
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND
From: Shaohui Xie
Updated the RCW for rev2.0 which uses new frequency settings as below:
Clock Configuration:
CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,
CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,
CPU8:1666.667 MHz, CPU9:1666.667 M
From: Shaohui Xie
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND
From: Shaohui Xie
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND
From: Shaohui Xie
Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO
access, this is due to an errata A-006260 on T4 rev1.0 which is fixed
on rev2.0, so remove the maximum value to use the default value for rev2.0.
Signed-off-by: Shaohui Xie
---
drivers/net/fm/memac_phy.c |
From: Shaohui Xie
A-007186: SerDes Ring VCO does not maintain lock throughout specified
temperature range.
Option 1 of the workaround states:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functiona
From: Shaohui Xie
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
or +70C/-80C when using XnVDD of 1.5 V). No issues are seen
From: Shaohui Xie
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
(or +70C/-80C when using XnVDD of 1.5 V). No issues are seen
From: Shaohui Xie
A U-boot CMD vdd_read is implemented to read Core voltage.
Signed-off-by: Shaohui Xie
---
board/freescale/t4qds/t4240qds.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
i
From: Shaohui Xie
When creating phy-handle property, an unsigned int value is created by
fdt_create_phandle, and memcpy is used to get the value, since DTS is
big endian, the value cannot be used directly on little endian SoCs,
it should be converted by cpu_to_fdt32.
Signed-off-by: Shaohui Xie
From: Shaohui Xie
This needed to init dpmac.
Signed-off-by: Shaohui Xie
---
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
From: Shaohui Xie
The phy can share driver with other aquantia PHYs, so we only added PHY
ID.
Signed-off-by: Shaohui Xie
---
drivers/net/phy/aquantia.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index ef4da4e..f9
From: Shaohui Xie
We don't disable unused FM1-DTSEC1 MAC node in FMAN v2 since its used
for MDIO, in FMAN v3, MDIO uses dedicated controller, so we can disable
the unused FM1-DTSEC1 MAC node to avoid it's being probed in kernel.
Signed-off-by: Shaohui Xie
---
drivers/net/fm/init.c | 4
1
From: Shaohui Xie
Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3
support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes
A/B/C/D are not available, updated the serdes table accordingly with
some minor fix.
Signed-off-by: Shaohui Xie
---
changes in v2:
re
From: Shaohui Xie
commit b8e5b07225 "Powerpc: eSDHC: Fix mmc read write err in uboot of
T4240QDS board", T4160 also needs this fix.
Signed-off-by: Shaohui Xie
---
drivers/mmc/fsl_esdhc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc
From: Shaohui Xie
To support on board Aquantia's PHY AQR405.
Signed-off-by: Shaohui Xie
---
include/configs/ls2085ardb.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index c1c1572..ec9297d 100644
--- a/include/configs/ls2085ard
From: Shaohui Xie
Fixes lsch2 SerDes registers define according to LS1043A RM Rev D.
Signed-off-by: Shaohui Xie
---
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 67 +++---
1 file changed, 47 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-laye
From: Shaohui Xie
Fixes lsch2 SerDes registers define according to LS1043A RM Rev D.
Signed-off-by: Shaohui Xie
---
changes in v2:
1. fixes indent.
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 67 +++---
1 file changed, 47 insertions(+), 20 deletions(-)
diff --git a/a
From: Shaohui Xie
This patch also exposes the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie
---
board/freescale/ls1043aqds/ddr.c| 19 ---
board/freescale/ls1043aqds/ls1043aqds.c | 10 ++
include/configs/ls1043aqds.h| 2 +-
3 files chan
From: Shaohui Xie
Current driver always performs a phy soft reset when connecting the phy
device, but soft reset is not always supported by a phy device, so
introduce a quirk PHY_BROKEN_RESET to let such a phy device to skip soft
reset. This commit uses 'flags' of phy device structure to store th
From: Shaohui Xie
Cortine phy cannot support soft reset, this commit implements probe
for Cortina PHY to tell phylib to skip phy soft reset by setting
PHY_BROKEN_RESET in flags.
Signed-off-by: Shaohui Xie
---
drivers/net/phy/cortina.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/
From: Shaohui Xie
T4160 and T4080 support same serdes options, which serdes 2 & 3 support 8
Lanes, same as T4240, but serdes 1 & 4 support only 4 Lanes, Lanes A, B,
C, D are not available, updated the serdes table accordingly with
some minor fix.
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu
From: Shaohui Xie
To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by
setting relative bit in SCFG_INTPCR register, because AQR105 interrupt
is low active but GIC accepts high active.
Signed-off-by: Shaohui Xie
---
board/freescale/ls1043ardb/ls1043ardb.c | 4
include/
From: Shaohui Xie
SCFG_USBPWRFAULT_DEDICATED instead of SCFG_USBPWRFAULT_SHARED should be
used for USB 3 & 2.
Signed-off-by: Shaohui Xie
---
board/freescale/ls1043aqds/ls1043aqds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c
From: Shaohui Xie
It's not always true that LPUART clock is CONFIG_SYS_CLK_FREQ, this
patch provides a weak function get_lpuart_clk, so that the clock can be
ovreride on a specific board which uses different clock for LPUART.
Signed-off-by: Shaohui Xie
---
drivers/serial/serial_lpuart.c | 7 ++
From: Shaohui Xie
LPUART0 is used by default, and it's using platform clock, if a different
clock is preferred, user can define CONFIG_LPUART_CLK.
Signed-off-by: Shaohui Xie
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-ls1046a-qds-lpuart.dts | 16 ++
arch/arm/dt
From: Shaohui Xie
The current value to check whether the PHY was configured has dependency
on MC, it expects MC to start PCS AN, this is not true during boot up,
so it should be changed to remove the dependency.
The PHY's register space should be restore to default after accessing
extended space
From: Shaohui Xie
The define CONFIG_FSL_SATA_V2 is missing, so SATA is not available
in U-boot.
Signed-off-by: Shaohui Xie
---
include/configs/P5040DS.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
index 371485f..e4a031a 100644
--- a
From: Shaohui Xie
We need following changes to make xfi work on B4:
1. set cross-point switch VSC3308 to use sfp config when running xfi;
2. add 10G interface check for xfi;
3. set phy address for xfi so the 10G ports can be registered by mdio;
Signed-off-by: Shaohui Xie
---
board/freescale/b4
From: Shaohui Xie
XFI does not work stable on current board, it's due to heat sink issue,
to make it work stable the board needs additional heat sink, enable two
XFI lanes only. Right now we do not have such an erratum for the issue,
so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it.
From: Suresh Gupta
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_am
From: Suresh Gupta
SerDes2 lanes EFGH either go to SFP or AMC riser card slot2.
By default AMC will be configured even if no hwconfig is specified.
To enable XFI via SFP use the below hwconfig:
fsl_b4860_serdes2:sfp_amc=sfp
Signed-off-by: Suresh Gupta
Signed-off-by: Poonam Aggrwal
Sig
From: Shaohui Xie
Since xfi has no phy, we delete the property "phy-handle" and use
a "fixed-link" property for a xfi port.
Signed-off-by: Shaohui Xie
---
board/freescale/b4860qds/eth_b4860qds.c | 38 +
1 file changed, 38 insertions(+)
diff --git a/board/freesc
From: Minghuan Lian
BRDCFG1_EMI1_SEL_MASK has been changed to 0x78, which contains
selection bits and connected status bit. So the Corresponding mux
value of RGMII is changed to BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN.
Signed-off-by: Minghuan Lian
Signed-off-by: Shaohui Xie
---
board/freesca
From: Shaohui Xie
This patch supports AQ1202, AQ2104, AQR105 PHY.
Signed-off-by: Shaohui Xie
---
drivers/net/phy/Makefile | 1 +
drivers/net/phy/aquantia.c | 156 +
drivers/net/phy/phy.c | 3 +
include/phy.h | 1 +
4 files c
From: Shaohui Xie
When compiling under 64 bit mode, there are warnings as below:
In file included from drivers/block/ahci.c:16:0:
drivers/block/ahci.c: In function 'ahci_reset':
./arch/arm/include/asm/io.h:72:28: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
#d
From: Shaohui Xie
When setting fixed-link property to DTS, the values should be converted
with using cpu_to_fdt32 so that to have correct value on little endian
Soc.
Signed-off-by: Shaohui Xie
---
board/freescale/ls1043aqds/eth.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(
From: Shaohui Xie
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low active
but GIC accepts high active.
Signed-off-by: Shaohui Xie
---
board/freescale/ls2080ardb/ls2080ardb.c | 4
include/configs/ls20
From: Shaohui Xie
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.
Signed-off-by: Shaohui Xie
---
changes in v2:
1. move Interrupt register offset define to immap_lsch3.
From: Shaohui Xie
Current driver always performs a phy soft reset when connecting the phy
device, but soft reset is not always supported by a phy device, so
introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip
soft reset. This commit uses 'flags' of phy device structure to sto
From: Shaohui Xie
Cortina phy cannot support soft reset, this commit implements probe
for Cortina PHY to tell phylib to skip phy soft reset by setting
PHY_FLAG_BROKEN_RESET in flags.
Signed-off-by: Shaohui Xie
Acked-by: Joe Hershberger
---
changes in v2:
1. use PHY_FLAG_BROKEN_RESET instead of
From: Shaohui Xie
LPUART0 is used by default, and it's using platform clock.
Signed-off-by: Shaohui Xie
---
changes in v2:
1. dropped CONFIG_LPUART_CLK.
2. uses CONFIG_SYS_FSL_DDR4 in defconfig.
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-ls1046a-qds-lpuart.dts | 16 +
From: Shaohui Xie
It's not always true that LPUART clock is CONFIG_SYS_CLK_FREQ, this
patch provides a weak function get_lpuart_clk, so that the clock can be
ovreride on a specific board which uses different clock for LPUART.
Signed-off-by: Shaohui Xie
---
changes in v2:
none.
drivers/serial/
From: Shaohui Xie
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.
Signed-off-by: Shaohui Xie
---
drivers/net/fm/eth.c | 32 ++--
From: Shaohui Xie
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.
Signed-off-by: Shaohui Xie
---
not sure what was wrong, the patch did not show in patchwork,
From: Shaohui Xie
Add following configs in header file:
CONFIG_SYS_GENERIC_BOARD
CONFIG_DISPLAY_BOARDINFO
Signed-off-by: Shaohui Xie
---
include/configs/P2041RDB.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 16f7525..ef062
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