On 05/07/2013 04:04 PM, Andy Fleming wrote:
On Mon, Mar 25, 2013 at 12:33 PM, York Sun york...@freescale.com
mailto:york...@freescale.com wrote:
From: Shaohui Xie shaohui@freescale.com
mailto:shaohui@freescale.com
When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined
before re-submitting.
On Mon, Mar 25, 2013 at 12:33 PM, York Sun york...@freescale.com
mailto:york...@freescale.com wrote:
From: Roy ZANG tie-fei.z...@freescale.com
mailto:tie-fei.z...@freescale.com
T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ
Add board detail function to print more individual board information.
Signed-off-by: York Sun york...@freescale.com
---
Change since v2: use __weak instead of a weak alias
common/cmd_bdinfo.c |5 +
1 file changed, 5 insertions(+)
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
pixis_reset help command prints the message without a new line \n,
which makes the prompt on the same line.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/common/pixis.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/common/pixis.c b
pixis_reset help command prints the message without a new line \n,
which makes the prompt on the same line.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/common/pixis.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/common/pixis.c b/board/freescale
On 01/30/2013 11:40 AM, Allen Martin wrote:
On Wed, Jan 30, 2013 at 10:37:30AM -0800, York Sun wrote:
On 01/24/2013 05:00 PM, Allen Martin wrote:
I think you can drop the RFC from your patch at this point.
Built on all tegra20 and tegra30 devices with USE_PRIVATE_LIBGCC.
Tested on seaboard
On 01/30/2013 02:53 PM, Allen Martin wrote:
On Wed, Jan 30, 2013 at 11:47:57AM -0800, York Sun wrote:
On 01/30/2013 11:40 AM, Allen Martin wrote:
On Wed, Jan 30, 2013 at 10:37:30AM -0800, York Sun wrote:
On 01/24/2013 05:00 PM, Allen Martin wrote:
I think you can drop the RFC from your patch
On 03/04/2013 01:38 PM, Tom Rini wrote:
On Wed, Jan 30, 2013 at 03:11:40PM -0800, York Sun wrote:
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.
All other #define, typedef and enum
P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/Makefile |4
arch/powerpc/cpu/mpc85xx/speed.c |3 +--
arch
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into hwconfig.h.
Signed-off-by: York Sun york...@freescale.com
On Fri, 2012-08-17 at 12:54 -0500, Kumar Gala wrote:
On Aug 15, 2012, at 7:53 PM, York Sun wrote:
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h | 88 -
1 files changed, 87 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch
From: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b
We have actual topology infomation to find out exactly which core is present.
Calculate the number of cores if not specified.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/cpu.c | 65
For the cores with multiple threads, we need to figure out which physical
core a thread belongs. To match the core ids, update PIR registers and
spin tables.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/cpu/mpc85xx/fdt.c
Some debug registers have non-zero default out of reset. If software is
not setting debug registers, skip writing to them to avoid unnecessary
overriding.
Also add debug messages for workarounds and debug registers.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/ddr
When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 25 +-
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 22 ++-
arch/powerpc
Faster DDR3 timing requires parameters exceeding previously defined
range. Extended parameters are fixed. Added some debug messages.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 51 ---
.../cpu/mpc8xxx/ddr
Required by JEDEC 79-3E for high speed DDR3.
Also change CSn disabled message to debug.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 28 +---
1 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/cpu
Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu.c | 12 +-
arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 12 ++
arch/powerpc/cpu/mpc8xxx/ddr
Add one more argument to call function readline_into_buffer().
Fix print SPD format for negative values.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu
Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/main.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu
Empty slot should be skipped when calculating CAS latency.
Signed-off-by: York Sun york...@freescale.com
---
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
b
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 39 ++-
arch/powerpc/cpu/mpc85xx/start.S
Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/speed.c |5 +++--
arch/powerpc/include/asm/immap_85xx.h |7 +++
2 files changed, 10 insertions(+), 2 deletions
Panic if the number of cores is more than CONFIG_MAX_CPUS because it will
surely overflow gd structure.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b
Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
Rework L2 initialization to get all clusters
E6500 doesn't allow cache inhibit TLB alias. Use the boot page translation
instead. The boot page is always cache inhibit.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/mp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu
, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have
PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.
PME and FMan blocks can take different PLLs, configured by RCW.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/speed.c | 138
Corenet 2nd generation Chassis has different RCW and registers for SerDes.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h | 99 +++--
1 files changed, 94 insertions
The QCSP registers are at offset 0x1000 for SoCs with QMan v3.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h | 19 ++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc
Expand the reference clock select to three bits
000: 100 MHz
001: 125 MHz
010: 156.25MHz
011: 150 MHz
100: 161.1328125 MHz
All others reserved
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |3 ++-
1 files changed, 2 insertions(+), 1 deletions
Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch
providers.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
arch/powerpc/cpu/mpc85xx/Makefile |3 +-
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 159
arch/powerpc/cpu/mpc85xx
From: Priyanka Jain priyanka.j...@freescale.com
-VSC8662 is Dual Port 10/100/1000Base-T Phy,
100Base-FX/1000/Base-X Gigabit Ethernt Transceiver Phy.
-Its register set and features are similar to
other Vitesse Phys
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: York
whereas VSC3308 has 8 input and 8
output ports.
Programming of these devices are performed by two-wire or four-wire serial
interface.
Signed-off-by: Shaveta Leekha shav...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/common/Makefile |1 +
board
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/include/asm/fsl_liodn.h |7 +
arch/powerpc/include/asm/fsl_portals.h |3 ++
arch/powerpc/include/asm/immap_85xx.h | 41 ++-
3 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/arch
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Andy Fleming aflem...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
arch/powerpc/cpu/mpc85xx/Makefile
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/cpu/mpc85xx/Makefile |3 +
arch/powerpc/cpu/mpc85xx/b4860_ids.c | 141 +
arch
From: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu.c |3 +++
arch/powerpc/include/asm/processor.h |1 +
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch
From: Kumar Gala ga...@kernel.crashing.org
In case more than 32 bit address is used, the EXT bit should be set.
Need to fix up address map for IFC #CS for 4, also need to move # of IFC
banks into config_mpc85xx.h
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: York Sun york
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into arch/powerpc/include/asm/config.h.
Signed-off-by: York Sun york
On Wed, 2012-08-22 at 11:18 -0500, Andy Fleming wrote:
On Fri, Aug 17, 2012 at 1:27 PM, York Sun york...@freescale.com wrote:
The QCSP registers are at offset 0x1000 for SoCs with QMan v3.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h | 19
On 08/24/2012 03:53 PM, Scott Wood wrote:
On 08/17/2012 01:27 PM, York Sun wrote:
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/cpu
On 08/24/2012 03:55 PM, Scott Wood wrote:
On 08/17/2012 01:27 PM, York Sun wrote:
E6500 doesn't allow cache inhibit TLB alias. Use the boot page translation
instead. The boot page is always cache inhibit.
We're not supposed to create such aliases on any PPC core.
We seem to have been using
On 09/02/2012 05:43 AM, Wolfgang Denk wrote:
Dear York Sun,
In message 1345226412.6510.38.camel@oslab-l1 you wrote:
On Fri, 2012-08-17 at 12:54 -0500, Kumar Gala wrote:
On Aug 15, 2012, at 7:53 PM, York Sun wrote:
Before proper environment is setup, we extract hwconfig and put
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into arch/powerpc/include/asm/config.h.
Signed-off-by: York Sun york
Add i2c write command to write data from memory to i2c devices.
Signed-off-by: York Sun york...@freescale.com
---
common/cmd_i2c.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 2cdc4ed..6099115
On 09/17/2012 06:36 PM, Tom Rini wrote:
On Mon, Sep 17, 2012 at 11:29:00PM +, sun york-R58495 wrote:
Tom,
It's like eeprom write but it writes to general devices, not specificly to
system eeprom. I would have to use i2c mw command a lot without this.
Right. I guess what I'm getting at
for calibration. Setting those registers to 0 may confuse
controllers in some cases. Instead, setting them to 0x together
with normal LAWs will guarantee the address is not mapped to DDR.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |4
On selected platforms, x4 DDR devices can be supported. Using x4 devices may
lower the performance, but generally they are available for higher density.
Tested on MT36JSF2G72PZ-1G9E1 RDIMM.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c|4
CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef.
Signed-off-by: York Sun york...@freescale.com
---
include/configs/t4qds.h | 68 ---
1 file changed, 68 deletions(-)
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/include/asm/config_mpc85xx.h |5 +
include/configs/B4860QDS.h|1 -
include/configs/P2041RDB.h
FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even
remote. In case none of them is defined, set it to null.
Signed-off-by: York Sun york...@freescale.com
---
drivers/net/fm/fm.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun york
The RCW print is common for all corenet platforms. Not necessary to ducplicate
in each board file.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu.c | 23 +++
board/freescale/b4860qds/b4860qds.c | 15 ---
board
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
arch
RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for
dual rank. Single- and quad-rank are not tested due to availability.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/t4qds/ddr.h | 19 +--
1 file changed, 9 insertions(+), 10 deletions
Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.
Signed-off-by: York Sun york
On 06/25/2013 02:24 PM, Wolfgang Denk wrote:
Entry to MAINTAINERS missing. And checkpatch reports a number of
Didn't know we are enforcing this. Will add.
warnings that need to be fixed:
- WARNING: quoted string split across lines
Noticed. How are we going to balance the long lines vs
On 06/26/2013 03:03 PM, Wolfgang Denk wrote:
Dear York Sun,
In message 1372263479-10588-1-git-send-email-york...@freescale.com you
wrote:
Add emulator support for T4240. Emulator has limited peripherals and
interfaces. Difference between emulator and T4240QDS includes:
ECC for DDR
On 06/27/2013 10:35 AM, Scott Wood wrote:
On 06/27/2013 12:30:25 PM, York Sun wrote:
On 06/26/2013 03:03 PM, Wolfgang Denk wrote:
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -538,6 +538,10 @@ Detlev Zundel d...@denx.de
inka4x0MPC5200
+York Sun york...@freescale.com
On 06/27/2013 10:51 AM, Wolfgang Denk wrote:
Dear York Sun,
In message 51cc76b1.6030...@freescale.com you wrote:
So what exactly are the changes compared to V1?
Added entry to MAINTAINERS
Fixed checkpatch warning
- WARNING: quoted string split across lines
- WARNING: Avoid unnecessary
From: James Yang james.y...@freescale.com
The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but
the mask omitted the LSB. This patch provides a 2-bit wide mask.
Signed-off-by: James Yang james.y...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu
Simon,
Your patch
commit 669dfc2ed8d853d6bcdcafa1de6aca22929465e5
Author: Simon Glass s...@chromium.org
Date: Mon Mar 11 06:30:27 2013 +
fdt: Ensure that libfdt_env.h comes from U-Boot
adds libfdt_env.h to HOSTCPPFLAGS. The causes a problem with one of our
older hosts. On the old
On 07/30/2013 02:17 PM, Simon Glass wrote:
Hi York,
On Tue, Jul 30, 2013 at 3:12 PM, York Sun york...@freescale.com
mailto:york...@freescale.com wrote:
Simon,
Your patch
commit 669dfc2ed8d853d6bcdcafa1de6aca22929465e5
Author: Simon Glass s...@chromium.org mailto:s
On 07/30/2013 02:29 PM, York Sun wrote:
On 07/30/2013 02:17 PM, Simon Glass wrote:
Hi York,
On Tue, Jul 30, 2013 at 3:12 PM, York Sun york...@freescale.com
mailto:york...@freescale.com wrote:
Simon,
Your patch
commit 669dfc2ed8d853d6bcdcafa1de6aca22929465e5
Author
Commit 669dfc2e adds libfdt_env.h to HOSTCPPFLAGS. It causes stdio.h
to be included before _GNU_SOURCE is defined in C files. On some old hosts
some prototypes are protected by #ifdef __USE_GNU, which is set when
_GNU_SOURCE is defined.
Signed-off-by: York Sun york...@freescale.com
---
Compiled
On 06/19/2013 12:48 AM, Николай Пузанов wrote:
---
arch/powerpc/cpu/mpc85xx/fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
---
1.8.1.2
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 24eb978..ece1336 100644
---
On 07/02/2013 04:05 AM, Sandeep Singh wrote:
Explicitly disabling unused IPs/blocks. This will lower
power consumption.
Signed-off-by: Sandeep Singh sand...@freescale.com
snip
+
+void cpu_device_disable()
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /*
From: Roy Zang tie-fei.z...@freescale.com
Fix the following build error caused by patch powerpc/pcie: add PCIe
version 3.x support:
pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function)
pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function)
Fix the lincese header introduced by the following patches
Add TWR-P10xx board support
Add T4240EMU target
IDT8T49N222A configuration code
Add C29x SoC support
Add support for C29XPCIE board
Signed-off-by: York Sun york...@freescale.com
---
This patch fixes the lincense header for the patches
Fix the license header introduced by the following patches
Add TWR-P10xx board support
Add T4240EMU target
IDT8T49N222A configuration code
Add C29x SoC support
Add support for C29XPCIE board
Signed-off-by: York Sun york...@freescale.com
---
Change since v1: Fix typo.
arch/powerpc/cpu/mpc85xx
/b4860qds: Add support for configuring SerDes1 Refclks
Xie Xiaobo (1):
powerpc/85xx: Add TWR-P10xx board support
York Sun (12):
powerpc/corenet: Move CONFIG_FSL_CORENET out of board header file
drivers/fm: Fix compiling error if FW location is not defined
mpc85xx: Base
On 08/11/2013 09:05 AM, feng...@phytium.com.cn wrote:
From: fenghua fenghua@ligen-virtual-machine.(none)
This patch provide u-boot with arm64 support. Currently, it works on
Foundation Model for armv8 or Fast Model for armv8.
Signed-off-by: fenghua fenghua@ligen-virtual-machine.(none)
It
On 07/25/2013 12:44 AM, ying.zh...@freescale.com wrote:
From: Ying Zhang b40...@freescale.com
Due to the nand SPL on some board(e.g. P1022DS)has a size limit, it can
not be more than 4K. So, the SPL cannot initialize the DDR with the SPD
code. This patch introduces TPL to enable a loader
On 07/25/2013 12:44 AM, ying.zh...@freescale.com wrote:
From: Ying Zhang b40...@freescale.com
Enable p1022ds to start from eSDHC with SPL.
Signed-off-by: Ying Zhang b40...@freescale.com
Ying,
Does this patch need anything out of this set? I can't get the following
targets built
On 07/26/2013 03:02 AM, Valentin Longchamp wrote:
If the DDR3 module supports industrial temperature range and requires
the x2 refresh rate for that temp range, the refresh period must be
3.9us instead of 7.8 us.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
On 07/26/2013 03:02 AM, Valentin Longchamp wrote:
If this #define stays in config_mpc85xx.h, the P2041 based boards must
define a lot of SRIO values even if they do not implement a SRIO device.
The #define is moved into the P2041RDB board config file where it is
used.
Signed-off-by:
On 07/26/2013 03:02 AM, Valentin Longchamp wrote:
This can be useful if we want to disable an interface in u-boot and
later reenable them, so that it looks available when trying to fix the
FDT or for the kernel.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
On 07/31/2013 08:31 AM, Shruti Kanetkar wrote:
Makes the startup output more consistent
Signed-off-by: Shruti Kanetkar shr...@freescale.com
Acked-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/cpu/mpc824x/cpu.c | 8 +++-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 8
On 07/26/2013 03:02 AM, Valentin Longchamp wrote:
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+ puts(Initializing);
+
+ if (fsl_use_spd()) {
+ puts(using SPD\n);
+ dram_size = fsl_ddr_sdram();
+ } else {
+
On 08/05/2013 03:43 AM, Ramneek Mehresh wrote:
Erratum-A006918 prevents internal UTMI dual phy pll inside T4240
rev 1.0 from starting sometimes. Workaround involves restarting
phy pll maximum seven times with 1ms delay in each loop
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
On 08/05/2013 03:43 AM, Ramneek Mehresh wrote:
Erratum-A006918 prevents internal UTMI phy pll from starting
sometimes. Workaround involves restarting phy pll maximum seven
times with 1ms delay in each loop. If pll still fails to start
after max retries, status property is set to
On 08/14/2013 06:48 AM, Tom Rini wrote:
On 08/13/2013 10:31 PM, Zhang Ying-B40530 wrote:
Hi, Tom, This patch hasn't been applied? I think it should be
applied early and it is needed by other patches of this set.
Thanks.
I expect that as part of the overall series, once ready, York will
On 08/05/2013 03:30 AM, Ramneek Mehresh wrote:
snip
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
new file mode 100644
index 000..88d6a1f
--- /dev/null
+++ b/include/fsl_usb.h
@@ -0,0 +1,80 @@
+/*
+ * Freescale USB Controller
+ *
+ * Copyright 2013 Freescale Semiconductor,
Replace license header with SPDX license identifier.
Replace GPL-2.0 with GPL-2.0+.
Signed-off-by: York Sun york...@freescale.com
---
include/fsl_usb.h | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 88d6a1f
hardcoded init for serdes block 1 2
York Sun (1):
include/fsl_usb.h: Cleanup license header
ramneek mehresh (2):
fsl/usb: Move USB internal phy definitions to fsl_usb.h
powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env
variables
arch/powerpc/cpu/mpc85xx/cpu_init.c
On 08/14/2013 01:30 PM, Sharma Bhupesh-B45370 wrote:
Hi York,
I guess with Andy no longer there as FSL u-boot maintainer, will the patch
below
go through you or Joe. If no one has an objection to this patch, can I get a
Acked-by and
can we queue it up for upstream.
Acked-by: York Sun
On 08/13/2013 11:01 PM, ying.zh...@freescale.com wrote:
From: Zhang Ying rock.ap.freescale.net
SPL defines CONFIG_SPL_BUILD but this does not percolate to the autoconf.mk
Makefile.
As a result the build breaks when CONFIG_SPL_BUILD is used in the
board-specific include
header file. With
On 08/13/2013 07:49 PM, Zhang Ying-B40530 wrote:
Hi, York,
Because a patch that this patch needed hasn't been applied, I Don't
know who should fix it:
http://patchwork.ozlabs.org/patch/252805/
Ying,
Please compile it on top of 85xx/master branch. I got this warning
spl.c: In
On 08/09/2013 03:41 AM, Shaohui Xie wrote:
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Tom,
I
On 08/16/2013 12:14 AM, ying.zh...@freescale.com wrote:
From: Ying Zhang b40...@freescale.com
SPL defines CONFIG_SPL_BUILD but this does not percolate to the autoconf.mk
Makefile.
As a result the build breaks when CONFIG_SPL_BUILD is used in the
board-specific include
header file. With
From: Shaohui Xie shaohui@freescale.com
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Resend for
On 08/09/2013 03:41 AM, Shaohui Xie wrote:
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes
On 08/19/2013 12:54 PM, Tom Rini wrote:
On Mon, Aug 19, 2013 at 02:47:53PM -0500, Scott Wood wrote:
On Mon, 2013-08-19 at 16:14 +0800, ying.zh...@freescale.com wrote:
From: Ying Zhang b40...@freescale.com
No. You added one line AFAICT. Preserve the original author here.
Indeed.
Do we
On 08/19/2013 03:04 PM, Tom Rini wrote:
On Mon, Aug 19, 2013 at 02:20:25PM -0700, York Sun wrote:
On 08/19/2013 12:54 PM, Tom Rini wrote:
On Mon, Aug 19, 2013 at 02:47:53PM -0500, Scott Wood wrote:
On Mon, 2013-08-19 at 16:14 +0800, ying.zh...@freescale.com wrote:
From: Ying Zhang b40
On 03/28/2013 03:46 AM, Ruchika Gupta wrote:
PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.
The Header file fsl_pamu.h and few functions in driver have been
Stefan,
Would you ack this patch? It has a minor change to
arch/powerpc/cpu/ppc4xx/cpu.c.
On 08/15/2013 09:25 AM, Shruti Kanetkar wrote:
Makes the startup output more consistent
Signed-off-by: Shruti Kanetkar shr...@freescale.com
Acked-by: Andy Fleming aflem...@freescale.com
---
On 08/14/2013 06:45 PM, Shengzhou Liu wrote:
CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK was needed only on
obsolete P1010RDB Rev.B non-formal board, not reproduced on
P1010RDB Rev.C and new P1010RDB-PB, now it's no longer needed.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
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