From: Chris Chen
Add new clock driver for MedaiTek MT8189 and compatible SoCs.
Signed-off-by: Chris Chen
Co-developed-by: David Lechner
Signed-off-by: David Lechner
---
drivers/clk/mediatek/Makefile |1 +
drivers/clk/mediatek/clk-mt8189.c | 1738 +
2 files changed, 1739 insertions(+)
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 5bede819c0d..a8be9adf18e 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o
obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
obj-$(CONFIG_TARGET_MT8188) += clk-mt8188.o
+obj-$(CONFIG_TARGET_MT8391) += clk-mt8189.o
obj-$(CONFIG_TARGET_MT8195) += clk-mt8195.o
obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o
obj-$(CONFIG_TARGET_MT8512) += clk-mt8512.o
diff --git a/drivers/clk/mediatek/clk-mt8189.c
b/drivers/clk/mediatek/clk-mt8189.c
new file mode 100644
index 000..093c4f2df86
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189.c
@@ -0,0 +1,1738 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2026 MediaTek Inc.
+ * Author: Chris Chen
+ * Author: David Lechner
+ */
+
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+/* TOPCK MUX SEL REG */
+#define CLK_CFG_UPDATE 0x0004
+#define CLK_CFG_UPDATE10x0008
+#define CLK_CFG_UPDATE20x000c
+#define VLP_CLK_CFG_UPDATE 0x0004
+#define CLK_CFG_0 0x0010
+#define CLK_CFG_0_SET 0x0014
+#define CLK_CFG_0_CLR 0x0018
+#define CLK_CFG_1 0x0020
+#define CLK_CFG_1_SET 0x0024
+#define CLK_CFG_1_CLR 0x0028
+#define CLK_CFG_2 0x0030
+#define CLK_CFG_2_SET 0x0034
+#define CLK_CFG_2_CLR 0x0038
+#define CLK_CFG_3 0x0040
+#define CLK_CFG_3_SET 0x0044
+#define CLK_CFG_3_CLR 0x0048
+#define CLK_CFG_4 0x0050
+#define CLK_CFG_4_SET 0x0054
+#define CLK_CFG_4_CLR 0x0058
+#define CLK_CFG_5 0x0060
+#define CLK_CFG_5_SET 0x0064
+#define CLK_CFG_5_CLR 0x0068
+#define CLK_CFG_6 0x0070
+#define CLK_CFG_6_SET 0x0074
+#define CLK_CFG_6_CLR 0x0078
+#define CLK_CFG_7 0x0080
+#define CLK_CFG_7_SET 0x0084
+#define CLK_CFG_7_CLR 0x0088
+#define CLK_CFG_8 0x0090
+#define CLK_CFG_8_SET 0x0094
+#define CLK_CFG_8_CLR 0x0098
+#define CLK_CFG_9 0x00A0
+#define CLK_CFG_9_SET 0x00A4
+#define CLK_CFG_9_CLR 0x00A8
+#define CLK_CFG_10 0x00B0
+#define CLK_CFG_10_SET 0x00B4
+#define CLK_CFG_10_CLR 0x00B8
+#define CLK_CFG_11 0x00C0
+#define CLK_CFG_11_SET 0x00C4
+#define CLK_CFG_11_CLR 0x00C8
+#define CLK_CFG_12 0x00D0
+#define CLK_CFG_12_SET 0x00D4
+#define CLK_CFG_12_CLR 0x00D8
+#define CLK_CFG_13 0x00E0
+#define CLK_CFG_13_SET 0x00E4
+#define CLK_CFG_13_CLR 0x00E8
+#define CLK_CFG_14 0x00F0
+#define CLK_CFG_14_SET 0x00F4
+#define CLK_CFG_14_CLR 0x00F8
+#define CLK_CFG_15 0x0100
+#define CLK_CFG_15_SET 0x0104
+#define CLK_CFG_15_CLR 0x0108
+#define CLK_CFG_16 0x0110
+#define CLK_CFG_16_SET 0x0114
+#define CLK_CFG_16_CLR 0x0118
+#define CLK_CFG_17 0x0180
+#define CLK_CFG_17_SET 0x0184
+#define CLK_CFG_17_CLR 0x0188
+#define CLK_CFG_18 0x0190
+#define CLK_CFG_18_SET 0x0194
+#define CLK_CFG_18_CLR 0x0198
+#define CLK_CFG_19 0x0240
+#define CLK_CFG_19_SET 0x0244
+#define CLK_CFG_19_CLR 0x0248
+#define CLK_AUDDIV_0 0x0320
+#define CLK_MISC_CFG_3 0x0510
+#define CLK_MISC_CF
