Re: [PATCH v3 1/2] spi: rockchip_sfc: Implement set_speed logic
On 2021/9/17 下午9:14, Jon Lin wrote:
Set clock related processing into set_speed logic. And Optimize
printing format.
Tested-by: Chris Morgan
Signed-off-by: Jon Lin
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes in v3:
- Remove useless headfile
- Fix misspelling
drivers/spi/rockchip_sfc.c | 82 ++
1 file changed, 39 insertions(+), 43 deletions(-)
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index 4e2b861f22..94222df5ce 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -116,6 +116,7 @@
/* Master trigger */
#define SFC_DMA_TRIGGER 0x80
+#define SFC_DMA_TRIGGER_START 1
/* Src or Dst addr for master */
#define SFC_DMA_ADDR 0x84
@@ -163,14 +164,12 @@
#define SFC_DMA_TRANS_THRETHOLD (0x40)
/* Maximum clock values from datasheet suggest keeping clock value under
- * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
- * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
+ * 150MHz. No minimum or average value is suggested.
*/
-#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
-#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
-#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
+#define SFC_MAX_SPEED (150 * 1000 * 1000)
struct rockchip_sfc {
+ struct udevice *dev;
void __iomem *regbase;
struct clk hclk;
struct clk clk;
@@ -197,8 +196,6 @@ static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
/* Still need to clear the masked interrupt from RISR */
writel(0x, sfc->regbase + SFC_ICLR);
- debug("reset\n");
-
return err;
}
@@ -261,15 +258,11 @@ static int rockchip_sfc_probe(struct udevice *bus)
#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(>hclk);
if (ret)
- debug("Enable ahb clock fail %s: %d\n", bus->name, ret);
+ dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n",
bus->name, ret);
ret = clk_enable(>clk);
if (ret)
- debug("Enable clock fail for %s: %d\n", bus->name, ret);
-
- ret = clk_set_rate(>clk, SFC_DEFAULT_SPEED_HZ);
- if (ret)
- debug("Could not set sfc clock for %s: %d\n", bus->name, ret);
+ dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n",
bus->name, ret);
#endif
ret = rockchip_sfc_init(sfc);
@@ -278,7 +271,8 @@ static int rockchip_sfc_probe(struct udevice *bus)
sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
sfc->version = rockchip_sfc_get_version(sfc);
- sfc->speed = SFC_DEFAULT_SPEED_HZ;
+ sfc->max_freq = SFC_MAX_SPEED;
+ sfc->dev = bus;
return 0;
@@ -411,11 +405,11 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
cmd |= plat->cs << SFC_CMD_CS_SHIFT;
- debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
- op->addr.nbytes, op->addr.buswidth,
- op->dummy.nbytes, op->dummy.buswidth);
- debug("ctrl=%x cmd=%x addr=%llx len=%x\n",
- ctrl, cmd, op->addr.val, len);
+ dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
+ op->addr.nbytes, op->addr.buswidth,
+ op->dummy.nbytes, op->dummy.buswidth);
+ dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
+ ctrl, cmd, op->addr.val, len);
writel(ctrl, sfc->regbase + SFC_CTRL);
writel(cmd, sfc->regbase + SFC_CMD);
@@ -492,7 +486,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct
rockchip_sfc *sfc, dma_addr_t d
{
writel(0x, sfc->regbase + SFC_ICLR);
writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
- writel(0x1, sfc->regbase + SFC_DMA_TRIGGER);
+ writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
return len;
}
@@ -500,7 +494,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct
rockchip_sfc *sfc, dma_addr_t d
static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
const struct spi_mem_op *op, u32 len)
{
- debug("xfer_poll len=%x\n", len);
+ dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);
if (op->data.dir == SPI_MEM_DATA_OUT)
return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
@@ -516,7 +510,7 @@ static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc
*sfc,
void *dma_buf;
int ret;
- debug("xfer_dma len=%x\n", len);
+ dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);
if (op->data.dir == SPI_MEM_DATA_OUT) {
dma_buf = (void *)op->data.buf.out;
@@ -564,33 +558,16 @@ static int rockchip_sfc_exec_op(struct spi_slave *mem,
u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
int ret;
-#if CONFIG_IS_ENABLED(CLK)
-
[PATCH v3 1/2] spi: rockchip_sfc: Implement set_speed logic
Set clock related processing into set_speed logic. And Optimize
printing format.
Tested-by: Chris Morgan
Signed-off-by: Jon Lin
---
Changes in v3:
- Remove useless headfile
- Fix misspelling
drivers/spi/rockchip_sfc.c | 82 ++
1 file changed, 39 insertions(+), 43 deletions(-)
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index 4e2b861f22..94222df5ce 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -116,6 +116,7 @@
/* Master trigger */
#define SFC_DMA_TRIGGER0x80
+#define SFC_DMA_TRIGGER_START 1
/* Src or Dst addr for master */
#define SFC_DMA_ADDR 0x84
@@ -163,14 +164,12 @@
#define SFC_DMA_TRANS_THRETHOLD(0x40)
/* Maximum clock values from datasheet suggest keeping clock value under
- * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
- * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
+ * 150MHz. No minimum or average value is suggested.
*/
-#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
-#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
-#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
+#define SFC_MAX_SPEED (150 * 1000 * 1000)
struct rockchip_sfc {
+ struct udevice *dev;
void __iomem *regbase;
struct clk hclk;
struct clk clk;
@@ -197,8 +196,6 @@ static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
/* Still need to clear the masked interrupt from RISR */
writel(0x, sfc->regbase + SFC_ICLR);
- debug("reset\n");
-
return err;
}
@@ -261,15 +258,11 @@ static int rockchip_sfc_probe(struct udevice *bus)
#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(>hclk);
if (ret)
- debug("Enable ahb clock fail %s: %d\n", bus->name, ret);
+ dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n",
bus->name, ret);
ret = clk_enable(>clk);
if (ret)
- debug("Enable clock fail for %s: %d\n", bus->name, ret);
-
- ret = clk_set_rate(>clk, SFC_DEFAULT_SPEED_HZ);
- if (ret)
- debug("Could not set sfc clock for %s: %d\n", bus->name, ret);
+ dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n",
bus->name, ret);
#endif
ret = rockchip_sfc_init(sfc);
@@ -278,7 +271,8 @@ static int rockchip_sfc_probe(struct udevice *bus)
sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
sfc->version = rockchip_sfc_get_version(sfc);
- sfc->speed = SFC_DEFAULT_SPEED_HZ;
+ sfc->max_freq = SFC_MAX_SPEED;
+ sfc->dev = bus;
return 0;
@@ -411,11 +405,11 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc
*sfc,
ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
cmd |= plat->cs << SFC_CMD_CS_SHIFT;
- debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
- op->addr.nbytes, op->addr.buswidth,
- op->dummy.nbytes, op->dummy.buswidth);
- debug("ctrl=%x cmd=%x addr=%llx len=%x\n",
- ctrl, cmd, op->addr.val, len);
+ dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
+ op->addr.nbytes, op->addr.buswidth,
+ op->dummy.nbytes, op->dummy.buswidth);
+ dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
+ ctrl, cmd, op->addr.val, len);
writel(ctrl, sfc->regbase + SFC_CTRL);
writel(cmd, sfc->regbase + SFC_CMD);
@@ -492,7 +486,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct
rockchip_sfc *sfc, dma_addr_t d
{
writel(0x, sfc->regbase + SFC_ICLR);
writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
- writel(0x1, sfc->regbase + SFC_DMA_TRIGGER);
+ writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
return len;
}
@@ -500,7 +494,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct
rockchip_sfc *sfc, dma_addr_t d
static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
const struct spi_mem_op *op, u32 len)
{
- debug("xfer_poll len=%x\n", len);
+ dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);
if (op->data.dir == SPI_MEM_DATA_OUT)
return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
@@ -516,7 +510,7 @@ static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc
*sfc,
void *dma_buf;
int ret;
- debug("xfer_dma len=%x\n", len);
+ dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);
if (op->data.dir == SPI_MEM_DATA_OUT) {
dma_buf = (void *)op->data.buf.out;
@@ -564,33 +558,16 @@ static int rockchip_sfc_exec_op(struct spi_slave *mem,
u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
int ret;
-#if CONFIG_IS_ENABLED(CLK)
- if (unlikely(mem->max_hz != sfc->speed)) {
- ret =
