Re: [U-Boot] [PATCH] bootm: Align cache flush begin address

[Bryan O'Donoghue]

On 13/04/18 17:27, Tom Rini wrote:

-   flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN));
+   flush_cache(ALIGN(load, ARCH_DMA_MINALIGN),
+   ALIGN(*load_end - load, ARCH_DMA_MINALIGN));

Am I wrong in thinking that we would want ALIGN_DOWN for load here?


No, we'll need to increase the length of the flush too.

I'll change this to an analog of

if (load != ALIGN_DOWN(load)) {
load_flush = ALIGN_DOWN(load);
load_flush_len += load - load_flush;
}

etc
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Re: [U-Boot] [PATCH] bootm: Align cache flush begin address

[Tom Rini]

On Fri, Apr 13, 2018 at 04:07:20PM +0100, Bryan O'Donoghue wrote:

> commit b4d956f6bc0f ("bootm: Align cache flush end address correctly")
> aligns the end address of the cache flush operation to a cache-line size to
> ensure lower-layers in the code accept the range provided and flush.
> 
> A similar action should be taken for the begin address of a cache flush
> operation. The load address may not be aligned to a cache-line boundary, so
> ensure the passed address is aligned.
> 
> Signed-off-by: Bryan O'Donoghue 
> Reported-by: Breno Matheus Lima 
> Cc: Simon Glass 
> ---
>  common/bootm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/common/bootm.c b/common/bootm.c
> index adb1213..45d140c 100644
> --- a/common/bootm.c
> +++ b/common/bootm.c
> @@ -447,7 +447,8 @@ static int bootm_load_os(bootm_headers_t *images, 
> unsigned long *load_end,
>   bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
>   return err;
>   }
> - flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN));
> + flush_cache(ALIGN(load, ARCH_DMA_MINALIGN),
> + ALIGN(*load_end - load, ARCH_DMA_MINALIGN));

Am I wrong in thinking that we would want ALIGN_DOWN for load here?

-- 
Tom


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[U-Boot] [PATCH] bootm: Align cache flush begin address

[Bryan O'Donoghue]

commit b4d956f6bc0f ("bootm: Align cache flush end address correctly")
aligns the end address of the cache flush operation to a cache-line size to
ensure lower-layers in the code accept the range provided and flush.

A similar action should be taken for the begin address of a cache flush
operation. The load address may not be aligned to a cache-line boundary, so
ensure the passed address is aligned.

Signed-off-by: Bryan O'Donoghue 
Reported-by: Breno Matheus Lima 
Cc: Simon Glass 
---
 common/bootm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/common/bootm.c b/common/bootm.c
index adb1213..45d140c 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -447,7 +447,8 @@ static int bootm_load_os(bootm_headers_t *images, unsigned 
long *load_end,
bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
return err;
}
-   flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN));
+   flush_cache(ALIGN(load, ARCH_DMA_MINALIGN),
+   ALIGN(*load_end - load, ARCH_DMA_MINALIGN));
 
debug("   kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end);
bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);
-- 
2.7.4

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