Re: [U-Boot] [PATCH 06/12] arm: socfpga: Add Altera Arria V DK support
On Sunday, January 18, 2015 at 07:19:40 AM, Dinh Nguyen wrote:
On 12/31/14 1:14 PM, Marek Vasut wrote:
Hi!
diff --git a/board/altera/socfpga/socfpga.c
b/board/altera/socfpga/socfpga.c index 459d82f..a9c330d 100644
--- a/board/altera/socfpga/socfpga.c
+++ b/board/altera/socfpga/socfpga.c
@@ -23,7 +23,14 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int checkboard(void)
{
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
puts(BOARD: Altera SoCFPGA Cyclone5 Board\n);
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+ puts(BOARD: Altera SoCFPGA Arria5 Board\n);
+#endif
+
return 0;
}
Do you need this change here only to get zapped in patch 11/12. No
objections really, just an observation.
You're right, I re-ordered the patches to cater for this. Thanks!
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 06/12] arm: socfpga: Add Altera Arria V DK support
On 12/31/14 1:14 PM, Marek Vasut wrote:
Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s...@denx.de
Cc: Vince Bridgers vbrid...@opensource.altera.com
---
arch/arm/Kconfig | 5 +
board/altera/socfpga/Kconfig | 16 +
board/altera/socfpga/iocsr_config.c | 688
+++
board/altera/socfpga/iocsr_config.h | 9 +
board/altera/socfpga/pinmux_config.c | 215 +++
board/altera/socfpga/socfpga.c | 7 +
configs/socfpga_arria5_defconfig | 3 +
include/configs/socfpga_arria5.h | 107 ++
8 files changed, 1050 insertions(+)
create mode 100644 configs/socfpga_arria5_defconfig
create mode 100644 include/configs/socfpga_arria5.h
snip
diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c
index 459d82f..a9c330d 100644
--- a/board/altera/socfpga/socfpga.c
+++ b/board/altera/socfpga/socfpga.c
@@ -23,7 +23,14 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int checkboard(void)
{
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
puts(BOARD: Altera SoCFPGA Cyclone5 Board\n);
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+ puts(BOARD: Altera SoCFPGA Arria5 Board\n);
+#endif
+
return 0;
}
Do you need this change here only to get zapped in patch 11/12. No
objections really, just an observation.
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
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Re: [U-Boot] [PATCH 06/12] arm: socfpga: Add Altera Arria V DK support
On Wed 2014-12-31 20:14:54, Marek Vasut wrote:
Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s...@denx.de
Cc: Vince Bridgers vbrid...@opensource.altera.com
---
arch/arm/Kconfig | 5 +
board/altera/socfpga/iocsr_config.c | 688
+++
board/altera/socfpga/iocsr_config.h | 9 +
board/altera/socfpga/pinmux_config.c | 215 +++
These are normally autogenerated, how does that work?
board/altera/socfpga/socfpga.c | 7 +
configs/socfpga_arria5_defconfig | 3 +
include/configs/socfpga_arria5.h | 107 ++
These look better. Can more defines be moved to common socfpga.h.
Thanks,
Pavel
diff --git a/include/configs/socfpga_arria5.h
b/include/configs/socfpga_arria5.h
new file mode 100644
index 000..668a91e
--- /dev/null
+++ b/include/configs/socfpga_arria5.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2014 Marek Vasut ma...@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
+#define __CONFIG_SOCFPGA_ARRIA5_H__
+
+#include asm/arch/socfpga_base_addrs.h
+#include ../../board/altera/socfpga/pinmux_config.h
+#include ../../board/altera/socfpga/iocsr_config.h
+#include ../../board/altera/socfpga/pll_config.h
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include config_cmd_default.h
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+#define CONFIG_REGEX /* Enable regular expression support */
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE0x4000 /* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE zImage
+#define CONFIG_BOOTARGS console=ttyS0,
__stringify(CONFIG_BAUDRATE)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_BOOTCOMMAND run ramboot
+#else
+#define CONFIG_BOOTCOMMAND run mmcload; run mmcboot
+#endif
+#define CONFIG_LOADADDR 0x8000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
+#define CONFIG_PHY_INTERFACE_MODEPHY_INTERFACE_MODE_RGMII
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV micrel-ksz9021-clk-skew
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV micrel-ksz9021-data-skew
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER Altera
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_arria5
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ verify=n\0 \
+ loadaddr= __stringify(CONFIG_SYS_LOAD_ADDR) \0 \
+ ramboot=setenv bootargs CONFIG_BOOTARGS ; \
+ bootm ${loadaddr} - ${fdt_addr}\0 \
+ bootimage=zImage\0 \
+ fdt_addr=100\0 \
+ fdtimage=socfpga.dtb\0 \
+ fsloadcmd=ext2load\0 \
+ bootm ${loadaddr} - ${fdt_addr}\0 \
+ mmcroot=/dev/mmcblk0p2\0 \
+ mmcboot=setenv bootargs CONFIG_BOOTARGS \
+ root=${mmcroot} rw rootwait; \
+ bootz ${loadaddr} - ${fdt_addr}\0 \
+ mmcload=mmc rescan; \
+ load mmc 0:1 ${loadaddr} ${bootimage}; \
+ load mmc 0:1 ${fdt_addr} ${fdtimage}\0 \
+ qspiroot=/dev/mtdblock0\0 \
+ qspirootfstype=jffs2\0 \
+ qspiboot=setenv bootargs CONFIG_BOOTARGS \
+ root=${qspiroot} rw rootfstype=${qspirootfstype};\
+ bootm ${loadaddr} - ${fdt_addr}\0
+
+/* The rest of the configuration is shared */
+#include configs/socfpga_common.h
+
+#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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Re: [U-Boot] [PATCH 06/12] arm: socfpga: Add Altera Arria V DK support
On Saturday, January 03, 2015 at 04:44:21 PM, Pavel Machek wrote: On Wed 2014-12-31 20:14:54, Marek Vasut wrote: Add support for the Altera Arria V development kit. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Pavel Machek pa...@denx.de Cc: Stefan Roese s...@denx.de Cc: Vince Bridgers vbrid...@opensource.altera.com --- arch/arm/Kconfig | 5 + board/altera/socfpga/iocsr_config.c | 688 +++ board/altera/socfpga/iocsr_config.h | 9 + board/altera/socfpga/pinmux_config.c | 215 +++ These are normally autogenerated, how does that work? I just pulled the default from rocketboards source. board/altera/socfpga/socfpga.c | 7 + configs/socfpga_arria5_defconfig | 3 + include/configs/socfpga_arria5.h | 107 ++ These look better. Can more defines be moved to common socfpga.h. I'd be much happier to move toward DT. The pinmux should be a particularly low hanging fruit. The defines here are added really only so the build would not complain until we move to DT. Basic sketch of that is already further down in the series, though for now that's U-Boot (not SPL) only. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 06/12] arm: socfpga: Add Altera Arria V DK support
Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s...@denx.de
Cc: Vince Bridgers vbrid...@opensource.altera.com
---
arch/arm/Kconfig | 5 +
board/altera/socfpga/Kconfig | 16 +
board/altera/socfpga/iocsr_config.c | 688 +++
board/altera/socfpga/iocsr_config.h | 9 +
board/altera/socfpga/pinmux_config.c | 215 +++
board/altera/socfpga/socfpga.c | 7 +
configs/socfpga_arria5_defconfig | 3 +
include/configs/socfpga_arria5.h | 107 ++
8 files changed, 1050 insertions(+)
create mode 100644 configs/socfpga_arria5_defconfig
create mode 100644 include/configs/socfpga_arria5.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5eb1d03..0a04cca 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -687,6 +687,11 @@ config TARGET_CM_FX6
select CPU_V7
select SUPPORT_SPL
+config TARGET_SOCFPGA_ARRIA5
+ bool Support socfpga_arria5
+ select CPU_V7
+ select SUPPORT_SPL
+
config TARGET_SOCFPGA_CYCLONE5
bool Support socfpga_cyclone5
select CPU_V7
diff --git a/board/altera/socfpga/Kconfig b/board/altera/socfpga/Kconfig
index fc42185..cbed8d6 100644
--- a/board/altera/socfpga/Kconfig
+++ b/board/altera/socfpga/Kconfig
@@ -13,3 +13,19 @@ config SYS_CONFIG_NAME
default socfpga_cyclone5
endif
+
+if TARGET_SOCFPGA_ARRIA5
+
+config SYS_BOARD
+ default socfpga
+
+config SYS_VENDOR
+ default altera
+
+config SYS_SOC
+ default socfpga
+
+config SYS_CONFIG_NAME
+ default socfpga_arria5
+
+endif
diff --git a/board/altera/socfpga/iocsr_config.c
b/board/altera/socfpga/iocsr_config.c
index b4b5ff8..c79aa6d 100644
--- a/board/altera/socfpga/iocsr_config.c
+++ b/board/altera/socfpga/iocsr_config.c
@@ -8,6 +8,7 @@
#include iocsr_config.h
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
const unsigned long iocsr_scan_chain0_table[((
CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x,
@@ -655,3 +656,690 @@ const unsigned long iocsr_scan_chain3_table[((
0x001F,
0x4100,
};
+#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+const unsigned long iocsr_scan_chain0_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x8000,
+ 0x00060180,
+ 0x1806,
+ 0x1860,
+ 0x00018060,
+ 0x06018060,
+ 0x4000,
+ 0x0C0300C0,
+ 0x0C03,
+ 0x0030,
+ 0x,
+ 0x,
+ 0x2000,
+ 0x,
+ 0x,
+ 0x0600,
+ 0x6018,
+ 0x01806018,
+ 0x1000,
+ 0xC030,
+ 0x0400,
+ 0x0300,
+ 0x300C,
+ 0x,
+ 0x0800,
+ 0x6018,
+ 0x01806000,
+ 0x0180,
+ 0x0006,
+ 0x1806,
+ 0x0400,
+ 0x300C,
+ 0x00C03000,
+ 0x00C0,
+ 0x0003,
+ 0x0C03,
+ 0x0200,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+ 0x0010,
+ 0x300C,
+ 0x30C0,
+ 0x00C0,
+ 0x000300C0,
+ 0x8000,
+ 0x00060180,
+ 0x1806,
+ 0x1800,
+ 0x0060,
+ 0x00018060,
+ 0x4000,
+ 0x000300C0,
+ 0x1000,
+ 0x0C00,
+ 0x0030,
+ 0xC030,
+ 0x2000,
+ 0x06018060,
+ 0x06018000,
+ 0x01FE,
+ 0xF800,
+ 0x0007,
+ 0x1000,
+ 0xC030,
+ 0x0300C000,
+ 0x0300,
+ 0x300C,
+ 0x300C,
+ 0x0800,
+ 0x6018,
+ 0x01806000,
+ 0x0180,
+ 0x0006,
+ 0x2000,
+ 0x0400,
+ 0x300C,
+ 0x0100,
+ 0x,
+ 0x0004,
+ 0x0C03,
+ 0x0200,
+ 0x1806,
+ 0x0080,
+ 0x,
+ 0x0002,
+ 0x0800,
+ 0x0100,
+ 0x1000,
+ 0x0040,
+ 0xC030,
+ 0x,
+ 0x0400,
+ 0x0080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+ 0x0010,
+ 0x4000,
+ 0x,
+ 0x0100,
+ 0x0004,
+ 0x8000,
+ 0x18060180,
+ 0x2000,
+ 0x,
+ 0x0080,
+ 0x0002,
+ 0x4000,
+ 0x0004,
+ 0x1000,
+ 0x,
+ 0x,
+ 0x0001,
+ 0x2000,
+
