Re: [U-Boot] [PATCH 1/6] spi: fsl_qspi: Fix DDR mode setting for latest iMX platforms

Hi Ye, On 14.08.19 12:08, Ye Li wrote: > On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller > is updated to have TDH field in FLSHCR register. According to reference > manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX > DDR delay logic won't be enabled.

Re: [U-Boot] [PATCH 1/6] spi: fsl_qspi: Fix DDR mode setting for latest iMX platforms

Please ignore the patch set. I will send out V2 to remove 2 patches. > On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller > is updated to have TDH field in FLSHCR register. According to reference > manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX > DDR

[U-Boot] [PATCH 1/6] spi: fsl_qspi: Fix DDR mode setting for latest iMX platforms

On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller is updated to have TDH field in FLSHCR register. According to reference manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX DDR delay logic won't be enabled. Another issue in DDR mode is the MCR register