Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
board/freescale/ls1021aqds/Makefile | 8 +
board/freescale/ls1021aqds/README | 112 +++
board/freescale/ls1021aqds/ddr.c | 169 +++
board/freescale/ls1021aqds/ddr.h | 64
board/freescale/ls1021aqds/ls1021aqds.c | 208 +
board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 +++
boards.cfg| 1 +
include/common.h | 5 +-
include/configs/ls1021aqds.h | 418 ++
9 files changed, 1017 insertions(+), 3 deletions(-)
create mode 100644 board/freescale/ls1021aqds/Makefile
create mode 100644 board/freescale/ls1021aqds/README
create mode 100644 board/freescale/ls1021aqds/ddr.c
create mode 100644 board/freescale/ls1021aqds/ddr.h
create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c
create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h
create mode 100644 include/configs/ls1021aqds.h
diff --git a/board/freescale/ls1021aqds/Makefile
b/board/freescale/ls1021aqds/Makefile
new file mode 100644
index 000..96c8c4c
--- /dev/null
+++ b/board/freescale/ls1021aqds/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1021aqds.o
+obj-y += ddr.o
diff --git a/board/freescale/ls1021aqds/README
b/board/freescale/ls1021aqds/README
new file mode 100644
index 000..c561776
--- /dev/null
+++ b/board/freescale/ls1021aqds/README
@@ -0,0 +1,112 @@
+Overview
+
+The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC.
+
+LS1021A SoC Overview
+--
+The QorIQ LS1 family, which includes the LS1021A communications processor,
+is built on Layerscape architecture, the industry's first software-aware,
+core-agnostic networking architecture to offer unprecedented efficiency
+and scale.
+
+A member of the value-performance tier, the QorIQ LS1021A processor provides
+extensive integration and power efficiency for fanless, small form factor
+enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
+running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
+performance of over 6,000, as well as virtualization support, advanced
+security features and the broadest array of high-speed interconnects and
+optimized peripheral features ever offered in a sub-3 W processor.
+
+The QorIQ LS1021A processor features an integrated LCD controller,
+CAN controller for implementing industrial protocols, DDR3L/4 running
+up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
+protection on both L1 and L2 caches. The LS1021A processor is pin- and
+software-compatible with the QorIQ LS1020A and LS1022A processors.
+
+The LS1021A SoC includes the following function and features:
+
+ - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
+ - Dual high-preformance ARM Cortex-A7 cores, each core includes:
+ - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC
protection)
+ - 512 Kbyte shared coherent L2 Cache (with ECC protection)
+ - NEON Co-processor (per core)
+ - 40-bit physical addressing
+ - Vector floating-point support
+ - ARM Core-Link CCI-400 Cache Coherent Interconnect
+ - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
+ supporting speeds up to 1600Mtps
+ - ECC and interleaving support
+ - VeTSEC Ethernet complex
+ - Up to 3x virtualized 10/100/1000 Ethernet controllers
+ - MII, RMII, RGMII, and SGMII support
+ - QoS, lossless flow control, and IEEE 1588 support
+ - 4-lane 6GHz SerDes
+ - High speed interconnect (4 SerDes lanes with are muxed for these protocol)
+ - Two PCI Express Gen2 controllers running at up to 5 GHz
+ - One Serial ATA 3.0 supporting 6 GT/s operation
+ - Two SGMII interfaces supporting 1000 Mbps
+ - Additional peripheral interfaces
+ - One high-speed USB 3.0 controller with integrated PHY and one high-speed
+ USB 2.00 controller with ULPI
+ - Integrated flash controller (IFC) with 16-bit interface
+ - Quad SPI NOR Flash
+ - One enhanced Secure digital host controller
+ - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface)
+ - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power
+ UARTs
+ - Three I2C controllers
+ - Eight FlexTimers four supporting PWM and four FlexCAN ports
+ - Four GPIO controllers supporting up to 109 general purpose I/O signals
+ - Integrated advanced audio block:
+ - Four synchronous audio interfaces (SAI)
+ - Sony/Philips Digital Interconnect Format (SPDIF)
+ - Asynchronous Sample Rate Converter (ASRC)
+ - Hardware based crypto offload engine
+
