Re: [U-Boot] [PATCH v1 03/19] phy: marvell: a3700: Don't create functional macro for each register
On 07.03.2018 22:52, Marek Behún wrote:
Currently there is for each register special functional macro, ie:
LANE_CFG1_ADDR(u)
GLOB_CLK_SRC_LO_ADDR(u)
...
where can be either PCIE or USB3.
Change this to one function PHY_ADDR(unit, addr). The code becomes:
PHY_ADDR(PCIE, LANE_CFG1)
PHY_ADDR(PCIE, GLOB_CLK_SRC_LO)
...
Signed-off-by: Marek Behun
---
drivers/phy/marvell/comphy_a3700.c | 105 ++---
drivers/phy/marvell/comphy_a3700.h | 92 +---
2 files changed, 89 insertions(+), 108 deletions(-)
diff --git a/drivers/phy/marvell/comphy_a3700.c
b/drivers/phy/marvell/comphy_a3700.c
index 505e0933a3..6506c134e2 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -141,72 +141,70 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
/*
* 1. Enable max PLL.
*/
- reg_set16(LANE_CFG1_ADDR(PCIE), bf_use_max_pll_rate, 0);
+ reg_set16(PHY_ADDR(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
/*
* 2. Select 20 bit SERDES interface.
*/
- reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE), bf_cfg_sel_20b, 0);
+ reg_set16(PHY_ADDR(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
/*
* 3. Force to use reg setting for PCIe mode
*/
- reg_set16(MISC_REG1_ADDR(PCIE), bf_sel_bits_pcie_force, 0);
+ reg_set16(PHY_ADDR(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
/*
* 4. Change RX wait
*/
- reg_set16(PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0x);
+ reg_set16(PHY_ADDR(PCIE, PWR_MGM_TIM1), 0x10C, 0x);
/*
* 5. Enable idle sync
*/
- reg_set16(UNIT_CTRL_ADDR(PCIE), 0x60 | rb_idle_sync_en, 0x);
+ reg_set16(PHY_ADDR(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0x);
/*
* 6. Enable the output of 100M/125M/500M clock
*/
- reg_set16(MISC_REG0_ADDR(PCIE),
+ reg_set16(PHY_ADDR(PCIE, MISC_REG0),
0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0x);
/*
* 7. Enable TX
*/
- reg_set(PHY_REF_CLK_ADDR, 0x1342, 0x);
+ reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0x);
/*
* 8. Check crystal jumper setting and program the Power and PLL
*Control accordingly
*/
if (get_ref_clk() == 40) {
- reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
- 0xFC63, 0x); /* 40 MHz */
+ /* 40 MHz */
+ reg_set16(PHY_ADDR(PCIE, PWR_PLL_CTRL), 0xFC63, 0x);
} else {
- reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
- 0xFC62, 0x); /* 25 MHz */
+ /* 25 MHz */
+ reg_set16(PHY_ADDR(PCIE, PWR_PLL_CTRL), 0xFC62, 0x);
}
/*
* 9. Override Speed_PLL value and use MAC PLL
*/
- reg_set16(KVCO_CAL_CTRL_ADDR(PCIE), 0x0040 | rb_use_max_pll_rate,
+ reg_set16(PHY_ADDR(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
0x);
/*
* 10. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT) {
- reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_txd_inv, 0);
- }
+ if (invert & PHY_POLARITY_TXD_INVERT)
+ reg_set16(PHY_ADDR(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT) {
- reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_rxd_inv, 0);
- }
+ if (invert & PHY_POLARITY_RXD_INVERT)
+ reg_set16(PHY_ADDR(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
/*
* 11. Release SW reset
*/
- reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE),
+ reg_set16(PHY_ADDR(PCIE, GLOB_PHY_CTRL0),
rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
bf_soft_rst | bf_mode_refdiv);
@@ -214,11 +212,11 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
udelay(PLL_SET_DELAY_US);
/* Assert PCLK enabled */
- ret = comphy_poll_reg(LANE_STAT1_ADDR(PCIE),/* address */
- rb_txdclk_pclk_en,/* value */
- rb_txdclk_pclk_en,/* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
- POLL_16B_REG);/* 16bit */
+ ret = comphy_poll_reg(PHY_ADDR(PCIE, LANE_STAT1), /* address */
+ rb_txdclk_pclk_en,/* value */
+ rb_txdclk_pclk_en,/* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_16B_REG);/* 16bit */
if (ret == 0)
printf("Failed to lock PCIe PLL\n");
@@ -322,7 +320,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
/* 0xd005c300 = 0x1001 */
[U-Boot] [PATCH v1 03/19] phy: marvell: a3700: Don't create functional macro for each register
Currently there is for each register special functional macro, ie:
LANE_CFG1_ADDR(u)
GLOB_CLK_SRC_LO_ADDR(u)
...
where can be either PCIE or USB3.
Change this to one function PHY_ADDR(unit, addr). The code becomes:
PHY_ADDR(PCIE, LANE_CFG1)
PHY_ADDR(PCIE, GLOB_CLK_SRC_LO)
...
Signed-off-by: Marek Behun
---
drivers/phy/marvell/comphy_a3700.c | 105 ++---
drivers/phy/marvell/comphy_a3700.h | 92 +---
2 files changed, 89 insertions(+), 108 deletions(-)
diff --git a/drivers/phy/marvell/comphy_a3700.c
b/drivers/phy/marvell/comphy_a3700.c
index 505e0933a3..6506c134e2 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -141,72 +141,70 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
/*
* 1. Enable max PLL.
*/
- reg_set16(LANE_CFG1_ADDR(PCIE), bf_use_max_pll_rate, 0);
+ reg_set16(PHY_ADDR(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
/*
* 2. Select 20 bit SERDES interface.
*/
- reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE), bf_cfg_sel_20b, 0);
+ reg_set16(PHY_ADDR(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
/*
* 3. Force to use reg setting for PCIe mode
*/
- reg_set16(MISC_REG1_ADDR(PCIE), bf_sel_bits_pcie_force, 0);
+ reg_set16(PHY_ADDR(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
/*
* 4. Change RX wait
*/
- reg_set16(PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0x);
+ reg_set16(PHY_ADDR(PCIE, PWR_MGM_TIM1), 0x10C, 0x);
/*
* 5. Enable idle sync
*/
- reg_set16(UNIT_CTRL_ADDR(PCIE), 0x60 | rb_idle_sync_en, 0x);
+ reg_set16(PHY_ADDR(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0x);
/*
* 6. Enable the output of 100M/125M/500M clock
*/
- reg_set16(MISC_REG0_ADDR(PCIE),
+ reg_set16(PHY_ADDR(PCIE, MISC_REG0),
0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0x);
/*
* 7. Enable TX
*/
- reg_set(PHY_REF_CLK_ADDR, 0x1342, 0x);
+ reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0x);
/*
* 8. Check crystal jumper setting and program the Power and PLL
*Control accordingly
*/
if (get_ref_clk() == 40) {
- reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
- 0xFC63, 0x); /* 40 MHz */
+ /* 40 MHz */
+ reg_set16(PHY_ADDR(PCIE, PWR_PLL_CTRL), 0xFC63, 0x);
} else {
- reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
- 0xFC62, 0x); /* 25 MHz */
+ /* 25 MHz */
+ reg_set16(PHY_ADDR(PCIE, PWR_PLL_CTRL), 0xFC62, 0x);
}
/*
* 9. Override Speed_PLL value and use MAC PLL
*/
- reg_set16(KVCO_CAL_CTRL_ADDR(PCIE), 0x0040 | rb_use_max_pll_rate,
+ reg_set16(PHY_ADDR(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
0x);
/*
* 10. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT) {
- reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_txd_inv, 0);
- }
+ if (invert & PHY_POLARITY_TXD_INVERT)
+ reg_set16(PHY_ADDR(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT) {
- reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_rxd_inv, 0);
- }
+ if (invert & PHY_POLARITY_RXD_INVERT)
+ reg_set16(PHY_ADDR(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
/*
* 11. Release SW reset
*/
- reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE),
+ reg_set16(PHY_ADDR(PCIE, GLOB_PHY_CTRL0),
rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
bf_soft_rst | bf_mode_refdiv);
@@ -214,11 +212,11 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
udelay(PLL_SET_DELAY_US);
/* Assert PCLK enabled */
- ret = comphy_poll_reg(LANE_STAT1_ADDR(PCIE),/* address */
- rb_txdclk_pclk_en,/* value */
- rb_txdclk_pclk_en,/* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
- POLL_16B_REG);/* 16bit */
+ ret = comphy_poll_reg(PHY_ADDR(PCIE, LANE_STAT1), /* address */
+ rb_txdclk_pclk_en,/* value */
+ rb_txdclk_pclk_en,/* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_16B_REG);/* 16bit */
if (ret == 0)
printf("Failed to lock PCIe PLL\n");
@@ -322,7 +320,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32
invert)
/* 0xd005c300 = 0x1001 */
/*
