Re: [U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-21 Thread Marek Vasut 
On 09/21/2016 03:53 AM, Chin Liang See wrote:
> On Wed, 2016-09-21 at 03:20 +0200, Marek Vasut wrote:
>> On 09/20/2016 08:05 AM, Chin Liang See wrote:
>>> To enable configuration of sdr.ctrlcfg.extratime1 register which
>>> enable
>>> extra clocks for read to write command timing. This is critical to
>>> ensure successful LPDDR2 interface
>>>
>>> Signed-off-by: Chin Liang See 
>>> Cc: Marek Vasut 
>>> Cc: Dinh Nguyen 
>>> ---
>>> Changes for v2
>>> - Removed v1 patches #2 to #9 as no boards are using LPDDR2
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
>>>  arch/arm/mach-socfpga/qts-filter.sh| 2 +-
>>>  arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +
>>>  drivers/ddr/altera/sdram.c | 3 +++
>>>  4 files changed, 20 insertions(+), 2 deletions(-)
>>> [...]
>>
>> I'd really like to avoid the ifdef, can we do that (fix all boards to
>> set the register to zero) ? Otherwise I'm fine with the patch.
>>
> 
> Ok I know where you come from. ifdef will cause some test challenge in
> term of coverage. In this case, let me fix all boards to zeroes.
Thanks


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-20 Thread Chin Liang See 
On Wed, 2016-09-21 at 03:20 +0200, Marek Vasut wrote:
> On 09/20/2016 08:05 AM, Chin Liang See wrote:
> > To enable configuration of sdr.ctrlcfg.extratime1 register which
> > enable
> > extra clocks for read to write command timing. This is critical to
> > ensure successful LPDDR2 interface
> > 
> > Signed-off-by: Chin Liang See 
> > Cc: Marek Vasut 
> > Cc: Dinh Nguyen 
> > ---
> > Changes for v2
> > - Removed v1 patches #2 to #9 as no boards are using LPDDR2
> > ---
> >  arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
> >  arch/arm/mach-socfpga/qts-filter.sh| 2 +-
> >  arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +
> >  drivers/ddr/altera/sdram.c | 3 +++
> >  4 files changed, 20 insertions(+), 2 deletions(-)
> > [...]
> 
> I'd really like to avoid the ifdef, can we do that (fix all boards to
> set the register to zero) ? Otherwise I'm fine with the patch.
> 

Ok I know where you come from. ifdef will cause some test challenge in
term of coverage. In this case, let me fix all boards to zeroes.

Thanks
Chin Liang

> 
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Re: [U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-20 Thread Marek Vasut 
On 09/20/2016 08:05 AM, Chin Liang See wrote:
> To enable configuration of sdr.ctrlcfg.extratime1 register which enable
> extra clocks for read to write command timing. This is critical to
> ensure successful LPDDR2 interface
> 
> Signed-off-by: Chin Liang See 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> ---
> Changes for v2
> - Removed v1 patches #2 to #9 as no boards are using LPDDR2
> ---
>  arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
>  arch/arm/mach-socfpga/qts-filter.sh| 2 +-
>  arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +
>  drivers/ddr/altera/sdram.c | 3 +++
>  4 files changed, 20 insertions(+), 2 deletions(-)
> [...]

I'd really like to avoid the ifdef, can we do that (fix all boards to
set the register to zero) ? Otherwise I'm fine with the patch.


-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Chin Liang See 
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
---
Changes for v2
- Removed v1 patches #2 to #9 as no boards are using LPDDR2
---
 arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
 arch/arm/mach-socfpga/qts-filter.sh| 2 +-
 arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +
 drivers/ddr/altera/sdram.c | 3 +++
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index f12bb84..b11228f 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
u32 dram_timing4;   /* 0x10 */
u32 lowpwr_timing;
u32 dram_odt;
-   u32 __padding0[4];
+   u32 extratime1;
+   u32 __padding0[3];
u32 dram_addrw; /* 0x2c */
u32 dram_if_width;  /* 0x30 */
u32 dram_dev_width;
@@ -88,6 +89,7 @@ struct socfpga_sdram_config {
u32 dram_timing4;
u32 lowpwr_timing;
u32 dram_odt;
+   u32 extratime1;
u32 dram_addrw;
u32 dram_if_width;
u32 dram_dev_width;
@@ -427,6 +429,10 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK 
\
 /* Field instance: sdr::ctrlgrp::dramsts   */
 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x0008
 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x0004
+/* Register template: sdr::ctrlgrp::extratime1 */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
 
 /* SDRAM width macro for configuration with ECC */
 #define SDRAM_WIDTH_32BIT_WITH_ECC 40
diff --git a/arch/arm/mach-socfpga/qts-filter.sh 
b/arch/arm/mach-socfpga/qts-filter.sh
index 050d6ba..1148a71 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -119,7 +119,7 @@ EOF
 # Filter out only the macros which are actually used by the code
 #
 grep_sdram_config() {
-   egrep "#define 
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CO!
 
NFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP!
 |CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_POR
TCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SD