CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters.
This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and
moves existing register space definaton of CCI-400 bus
from immap_lsch2 to fsl_immap, so that it can be used
for both chasis 2 and chasis 3.
"CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET
is introduced in Kconfig
Signed-off-by: Ashish Kumar
Signed-off-by: Prabhakar Kushwaha
---
v3:
This is v3 for https://patchwork.ozlabs.org/patch/731464/
v4:
Header file included in middle of the file in cpu.c
v5:
Moving ls1021aqds to 2/3-armv7 of this patch-set
README | 9
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 13 ++
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 1 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 10 +++--
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 49 -
board/freescale/ls1012afrdm/ls1012afrdm.c | 4 +-
board/freescale/ls1012aqds/ls1012aqds.c| 4 +-
board/freescale/ls1012ardb/ls1012ardb.c| 3 +-
include/fsl_immap.h| 51 ++
9 files changed, 88 insertions(+), 56 deletions(-)
diff --git a/README b/README
index 3735916..a66a7ae 100644
--- a/README
+++ b/README
@@ -312,6 +312,15 @@ Many of the options are named exactly as the corresponding
Linux
kernel configuration options. The intention is to make it easier to
build a config tool - later.
+- ARM Platform Bus Type(CCI):
+ CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
+ provides full cache coherency between two clusters of multi-core
+ CPUs and I/O coherency for devices and I/O masters
+
+ CONFIG_SYS_FSL_HAS_CCI400
+
+ Defined For SoC that has cache coherent interconnect
+ CCN-400
The following options need to be configured:
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5825f9b..1132969 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -84,6 +84,7 @@ config ARCH_LS2080A
config FSL_LSCH2
bool
+ select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_BE
@@ -247,6 +248,15 @@ config QSPI_AHB_INIT
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
bus for those flashes to support the full QSPI flash size.
+config SYS_CCI400_OFFSET
+ hex "Offset for CCI400 base"
+ depends on SYS_FSL_HAS_CCI400
+ default 0x309 if ARCH_LS1088A
+ default 0x18 if FSL_LSCH2
+ help
+ Offset for CCI400 base
+ CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
@@ -254,6 +264,9 @@ config SYS_FSL_IFC_BANK_COUNT
default 4 if ARCH_LS1046A
default 8 if ARCH_LS2080A
+config SYS_FSL_HAS_CCI400
+ bool
+
config SYS_FSL_HAS_DP_DDR
bool
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c6fede3..ec58065 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include
#include
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index aee1ffa..ddb7d82 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -285,7 +286,8 @@ static void erratum_a008850_early(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 1 of 2 */
- struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */
@@ -304,7 +306,8 @@ void erratum_a008850_post(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 2 of 2 */
- struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
u32 tmp;
@@ -439,7 +442,8 @@ int setup_chip_volt(void)
void fsl_lsch2_early_init_f(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS
