CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters.

This patch add new CONFIG defination "FSL_SYS_HAS_CCI400" and
removes register space definaton of CCI-400 bus from
immap_ls102xa to fsl_immap, since same is defined there already

"CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET
is introduced in Kconfig

Signed-off-by: Ashish Kumar <ashish.ku...@nxp.com>
---
v3: 
 This is v3 for https://patchwork.ozlabs.org/patch/731464/
v4:
 No change
v5:
 Moving ls1021aqds here

 arch/arm/cpu/armv7/ls102xa/Kconfig                | 12 ++++++
 arch/arm/cpu/armv7/ls102xa/soc.c                  |  3 +-
 arch/arm/include/asm/arch-ls102xa/config.h        |  1 -
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 49 +----------------------
 board/freescale/ls1021aqds/ls1021aqds.c           |  9 +++--
 5 files changed, 22 insertions(+), 52 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 6a013b2..61dd522 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
+       select SYS_FSL_HAS_CCI400
        select SYS_FSL_SRDS_1
        select SYS_HAS_SERDES
        select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -48,9 +49,20 @@ config SECURE_BOOT
                Enable Freescale Secure Boot feature. Normally selected
                by defconfig. If unsure, do not change.
 
+config SYS_CCI400_OFFSET
+       hex "Offset for CCI400 base"
+       depends on SYS_FSL_HAS_CCI400
+       default 0x180000
+       help
+         Offset for CCI400 base.
+         CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_HAS_CCI400
+       bool
+
 config SYS_FSL_SRDS_1
        bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index b84a1a6..c043b82 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -80,7 +80,8 @@ void erratum_a010315(void)
 int arch_soc_init(void)
 {
        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+                                       CONFIG_SYS_CCI400_OFFSET);
        unsigned int major;
 
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index fc954c5..ff0fc47 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -20,7 +20,6 @@
 
 #define SYS_FSL_GIC_ADDR                       (CONFIG_SYS_IMMR + 0x00400000)
 #define CONFIG_SYS_FSL_DDR_ADDR                        (CONFIG_SYS_IMMR + 
0x00080000)
-#define CONFIG_SYS_CCI400_ADDR                 (CONFIG_SYS_IMMR + 0x00180000)
 #define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x00530000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x00560000)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..1415b0b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -6,6 +6,7 @@
 
 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_
 #define __ASM_ARCH_LS102XA_IMMAP_H_
+#include <fsl_immap.h>
 
 #define SVR_MAJ(svr)           (((svr) >>  4) & 0xf)
 #define SVR_MIN(svr)           (((svr) >>  0) & 0xf)
@@ -374,53 +375,7 @@ struct ccsr_serdes {
        u8      res_a00[0x1000-0xa00];  /* from 0xa00 to 0xfff */
 };
 
-#define CCI400_CTRLORD_TERM_BARRIER    0x00000008
-#define CCI400_CTRLORD_EN_BARRIER      0
-#define CCI400_SHAORD_NON_SHAREABLE    0x00000002
-#define CCI400_DVM_MESSAGE_REQ_EN      0x00000002
-#define CCI400_SNOOP_REQ_EN            0x00000001
-
-/* CCI-400 registers */
-struct ccsr_cci400 {
-       u32 ctrl_ord;                   /* Control Override */
-       u32 spec_ctrl;                  /* Speculation Control */
-       u32 secure_access;              /* Secure Access */
-       u32 status;                     /* Status */
-       u32 impr_err;                   /* Imprecise Error */
-       u8 res_14[0x100 - 0x14];
-       u32 pmcr;                       /* Performance Monitor Control */
-       u8 res_104[0xfd0 - 0x104];
-       u32 pid[8];                     /* Peripheral ID */
-       u32 cid[4];                     /* Component ID */
-       struct {
-               u32 snoop_ctrl;         /* Snoop Control */
-               u32 sha_ord;            /* Shareable Override */
-               u8 res_1008[0x1100 - 0x1008];
-               u32 rc_qos_ord;         /* read channel QoS Value Override */
-               u32 wc_qos_ord;         /* read channel QoS Value Override */
-               u8 res_1108[0x110c - 0x1108];
-               u32 qos_ctrl;           /* QoS Control */
-               u32 max_ot;             /* Max OT */
-               u8 res_1114[0x1130 - 0x1114];
-               u32 target_lat;         /* Target Latency */
-               u32 latency_regu;       /* Latency Regulation */
-               u32 qos_range;          /* QoS Range */
-               u8 res_113c[0x2000 - 0x113c];
-       } slave[5];                     /* Slave Interface */
-       u8 res_6000[0x9004 - 0x6000];
-       u32 cycle_counter;              /* Cycle counter */
-       u32 count_ctrl;                 /* Count Control */
-       u32 overflow_status;            /* Overflow Flag Status */
-       u8 res_9010[0xa000 - 0x9010];
-       struct {
-               u32 event_select;       /* Event Select */
-               u32 event_count;        /* Event Count */
-               u32 counter_ctrl;       /* Counter Control */
-               u32 overflow_status;    /* Overflow Flag Status */
-               u8 res_a010[0xb000 - 0xa010];
-       } pcounter[4];                  /* Performance Counter */
-       u8 res_e004[0x10000 - 0xe004];
-};
+
 
 /* AHCI (sata) register map */
 struct ccsr_ahci {
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index d81d8ab..8b3f4ad 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -204,7 +204,8 @@ int board_early_init_f(void)
 #ifdef CONFIG_SPL_BUILD
 void board_init_f(ulong dummy)
 {
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+                                       CONFIG_SYS_CCI400_OFFSET);
        unsigned int major;
 
 #ifdef CONFIG_NAND_BOOT
@@ -425,7 +426,8 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+                                       CONFIG_SYS_CCI400_OFFSET);
        unsigned int major;
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
@@ -460,7 +462,8 @@ int board_init(void)
 #if defined(CONFIG_DEEP_SLEEP)
 void board_sleep_prepare(void)
 {
-       struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+       struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+                                               CONFIG_SYS_CCI400_OFFSET);
        unsigned int major;
 
        major = get_soc_major_rev();
-- 
2.7.4

_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Reply via email to