We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v4:
- Isolated maskbit changes.
Changes since v3:
- New patch.
arch/arm/cpu/armv7/exynos/clock.c | 151 --
1 file changed, 78 insertions(+), 73 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index f19fb5c..3884d4b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -21,79 +21,83 @@
*/
struct clk_bit_info {
enum periph_id id;
+ int32_t src_mask;
+ int32_t div_mask;
+ int32_t prediv_mask;
int8_t src_bit;
int8_t div_bit;
int8_t prediv_bit;
};
-/* periph_id src_bit div_bit prediv_bit */
static struct clk_bit_info exynos5_bit_info[] = {
- {PERIPH_ID_UART0, 0, 0, -1},
- {PERIPH_ID_UART1, 4, 4, -1},
- {PERIPH_ID_UART2, 8, 8, -1},
- {PERIPH_ID_UART3, 12, 12, -1},
- {PERIPH_ID_I2C0,-1, 24, 0},
- {PERIPH_ID_I2C1,-1, 24, 0},
- {PERIPH_ID_I2C2,-1, 24, 0},
- {PERIPH_ID_I2C3,-1, 24, 0},
- {PERIPH_ID_I2C4,-1, 24, 0},
- {PERIPH_ID_I2C5,-1, 24, 0},
- {PERIPH_ID_I2C6,-1, 24, 0},
- {PERIPH_ID_I2C7,-1, 24, 0},
- {PERIPH_ID_SPI0,16, 0, 8},
- {PERIPH_ID_SPI1,20, 16, 24},
- {PERIPH_ID_SPI2,24, 0, 8},
- {PERIPH_ID_SDMMC0, 0, 0, 8},
- {PERIPH_ID_SDMMC1, 4, 16, 24},
- {PERIPH_ID_SDMMC2, 8, 0, 8},
- {PERIPH_ID_SDMMC3, 12, 16, 24},
- {PERIPH_ID_I2S0,0, 0, 4},
- {PERIPH_ID_I2S1,4, 12, 16},
- {PERIPH_ID_SPI3,0, 0, 4},
- {PERIPH_ID_SPI4,4, 12, 16},
- {PERIPH_ID_SDMMC4, 16, 0, 8},
- {PERIPH_ID_PWM0,24, 0, -1},
- {PERIPH_ID_PWM1,24, 0, -1},
- {PERIPH_ID_PWM2,24, 0, -1},
- {PERIPH_ID_PWM3,24, 0, -1},
- {PERIPH_ID_PWM4,24, 0, -1},
-
- {PERIPH_ID_NONE,-1, -1, -1},
+ /* periph ids_mask d_mask p_mask s_bit d_bit p_bit */
+ {PERIPH_ID_UART0, 0xf,0xf,-1, 0, 0, -1},
+ {PERIPH_ID_UART1, 0xf,0xf,-1, 4, 4, -1},
+ {PERIPH_ID_UART2, 0xf,0xf,-1, 8, 8, -1},
+ {PERIPH_ID_UART3, 0xf,0xf,-1, 12, 12, -1},
+ {PERIPH_ID_I2C0,-1, 0x7,0x7,-1, 24, 0},
+ {PERIPH_ID_I2C1,-1, 0x7,0x7,-1, 24, 0},
+ {PERIPH_ID_I2C2,-1, 0x7,0x7,-1, 24, 0},
+ {PERIPH_ID_I2C3,-1, 0x7,0x7,-1, 24, 0},
+ {PERIPH_ID_I2C4,-1, 0x7,0x7,-1, 24, 0},
+ {PERIPH_ID_I2C5,-1, 0x7,0x7,-1, 24, 0},
+ {PERIPH_ID_I2C6,-1, 0x7,0x7,-1, 24, 0},
+ {PERIPH_ID_I2C7,-1, 0x7,0x7,-1, 24, 0},
+ {PERIPH_ID_SPI0,0xf,0xf,0xff, 16, 0, 8},
+ {PERIPH_ID_SPI1,0xf,0xf,0xff, 20, 16, 24},
+ {PERIPH_ID_SPI2,0xf,0xf,0xff, 24, 0, 8},
+ {PERIPH_ID_SDMMC0, 0xf,0xf,0xff, 0, 0, 8},
+ {PERIPH_ID_SDMMC1, 0xf,0xf,0xff, 4, 16, 24},
+ {PERIPH_ID_SDMMC2, 0xf,0xf,0xff, 8, 0, 8},
+ {PERIPH_ID_SDMMC3, 0xf,0xf,0xff, 12, 16, 24},
+ {PERIPH_ID_I2S0,0xf,0xf,0xff, 0, 0, 4},
+ {PERIPH_ID_I2S1,0xf,0xf,0xff, 4, 12, 16},
+ {PERIPH_ID_SPI3,0xf,0xf,0xff, 0, 0, 4},
+ {PERIPH_ID_SPI4,0xf,0xf,0xff, 4, 12, 16},
+ {PERIPH_ID_SDMMC4, 0xf,0xf,0xff, 16, 0, 8},
+ {PERIPH_ID_PWM0,0xf,0xf,-1, 24, 0, -1},
+ {PERIPH_ID_PWM1,0xf,0xf,-1, 24, 0, -1},
+ {PERIPH_ID_PWM2,0xf,0xf,-1, 24, 0, -1},
+ {PERIPH_ID_PWM3,0xf,0xf,-1, 24, 0, -1},
+ {PERIPH_ID_PWM4,0xf,0xf,-1, 24, 0, -1},
+
+ {PERIPH_ID_NONE,-1, -1, -1, -1, -1, -1},
};
