RE: [PATCH] stm32mp1: add 800 MHz profile support

2020-03-24 Thread Patrick DELAUNAY
Hi,

> From: Patrick DELAUNAY 
> Sent: mercredi 26 février 2020 11:27
> 
> The STM32MP1 series is available in 3 different lines which are pin-to-pin
> compatible:
> - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz,
>   3D GPU, DSI display interface and CAN FD
> - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz
>   and CAN FD
> - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
> 
> Each line comes with a security option (cryptography & secure boot) & a 
> Cortex-A
> frequency option :
> 
> - A : Cortex-A7 @ 650 MHz
> - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
> - D : Cortex-A7 @ 800 MHz
> - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
> 
> This patch adds the support of STM32MP15xD and STM32MP15xF in U-Boot.
> 
> Signed-off-by: Patrick Delaunay 
> ---


Applied to u-boot-stm/next, thanks!

Regards

Patrick


Re: [PATCH] stm32mp1: add 800 MHz profile support

2020-03-18 Thread Patrice CHOTARD

On 2/26/20 11:26 AM, Patrick Delaunay wrote:
> The STM32MP1 series is available in 3 different lines which are pin-to-pin
> compatible:
> - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz,
>   3D GPU, DSI display interface and CAN FD
> - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz
>   and CAN FD
> - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
>
> Each line comes with a security option (cryptography & secure boot)
> & a Cortex-A frequency option :
>
> - A : Cortex-A7 @ 650 MHz
> - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
> - D : Cortex-A7 @ 800 MHz
> - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
>
> This patch adds the support of STM32MP15xD and STM32MP15xF in U-Boot.
>
> Signed-off-by: Patrick Delaunay 
> ---
>
>  arch/arm/mach-stm32mp/cpu.c| 18 ++
>  arch/arm/mach-stm32mp/fdt.c|  7 +++
>  arch/arm/mach-stm32mp/include/mach/sys_proto.h |  8 +++-
>  doc/board/st/stm32mp1.rst  |  8 
>  4 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
> index 9c5e0448ce..9aa5794334 100644
> --- a/arch/arm/mach-stm32mp/cpu.c
> +++ b/arch/arm/mach-stm32mp/cpu.c
> @@ -285,18 +285,36 @@ void get_soc_name(char name[SOC_NAME_SIZE])
>  
>   /* MPUs Part Numbers */
>   switch (get_cpu_type()) {
> + case CPU_STM32MP157Fxx:
> + cpu_s = "157F";
> + break;
> + case CPU_STM32MP157Dxx:
> + cpu_s = "157D";
> + break;
>   case CPU_STM32MP157Cxx:
>   cpu_s = "157C";
>   break;
>   case CPU_STM32MP157Axx:
>   cpu_s = "157A";
>   break;
> + case CPU_STM32MP153Fxx:
> + cpu_s = "153F";
> + break;
> + case CPU_STM32MP153Dxx:
> + cpu_s = "153D";
> + break;
>   case CPU_STM32MP153Cxx:
>   cpu_s = "153C";
>   break;
>   case CPU_STM32MP153Axx:
>   cpu_s = "153A";
>   break;
> + case CPU_STM32MP151Fxx:
> + cpu_s = "151F";
> + break;
> + case CPU_STM32MP151Dxx:
> + cpu_s = "151D";
> + break;
>   case CPU_STM32MP151Cxx:
>   cpu_s = "151C";
>   break;
> diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c
> index a3db86dc46..3ee7d6a833 100644
> --- a/arch/arm/mach-stm32mp/fdt.c
> +++ b/arch/arm/mach-stm32mp/fdt.c
> @@ -244,6 +244,8 @@ int ft_system_setup(void *blob, bd_t *bd)
>   get_soc_name(name);
>  
>   switch (cpu) {
> + case CPU_STM32MP151Fxx:
> + case CPU_STM32MP151Dxx:
>   case CPU_STM32MP151Cxx:
>   case CPU_STM32MP151Axx:
>   stm32_fdt_fixup_cpu(blob, name);
> @@ -251,6 +253,8 @@ int ft_system_setup(void *blob, bd_t *bd)
>   soc = fdt_path_offset(blob, "/soc");
>   stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
>   /* fall through */
> + case CPU_STM32MP153Fxx:
> + case CPU_STM32MP153Dxx:
>   case CPU_STM32MP153Cxx:
>   case CPU_STM32MP153Axx:
>   stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
> @@ -261,8 +265,11 @@ int ft_system_setup(void *blob, bd_t *bd)
>   }
>  
>   switch (cpu) {
> + case CPU_STM32MP157Dxx:
>   case CPU_STM32MP157Axx:
> + case CPU_STM32MP153Dxx:
>   case CPU_STM32MP153Axx:
> + case CPU_STM32MP151Dxx:
>   case CPU_STM32MP151Axx:
>   stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name);
>   stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name);
> diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h 
> b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
> index 065b7b2856..1617126bea 100644
> --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
> +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
> @@ -3,13 +3,19 @@
>   * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
>   */
>  
> -/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/
> +/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) */
>  #define CPU_STM32MP157Cxx0x0500
>  #define CPU_STM32MP157Axx0x0501
>  #define CPU_STM32MP153Cxx0x0524
>  #define CPU_STM32MP153Axx0x0525
>  #define CPU_STM32MP151Cxx0x052E
>  #define CPU_STM32MP151Axx0x052F
> +#define CPU_STM32MP157Fxx0x0580
> +#define CPU_STM32MP157Dxx0x0581
> +#define CPU_STM32MP153Fxx0x05A4
> +#define CPU_STM32MP153Dxx0x05A5
> +#define CPU_STM32MP151Fxx0x05AE
> +#define CPU_STM32MP151Dxx0x05AF
>  
>  /* return CPU_STMP32MP...Xxx constants */
>  u32 get_cpu_type(void);
> diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
> index ee42af6579..b7a0fbfd03 100644
> ---