Re: [U-Boot] [PATCH] riscv: cache: Implement i/dcache [status, enable, disable]

2018-10-30 Thread Auer, Lukas
Hi Rick, On Tue, 2018-10-30 at 10:48 +0800, Rick Chen wrote: > Auer, Lukas 於 2018年10月29日 週一 > 下午8:13寫道： > > > > Hi Rick, > > > > On Mon, 2018-10-29 at 11:16 +0800, Rick Chen wrote: > > > Auer, Lukas 於 2018年10月27日 週六 > > > 上午12:32寫道： > > > > > > > > Hi Rick, > > > > > > > > On Mon,

Re: [U-Boot] [PATCH] riscv: cache: Implement i/dcache [status, enable, disable]

2018-10-29 Thread Rick Chen
Auer, Lukas 於 2018年10月29日 週一 下午8:13寫道： > > Hi Rick, > > On Mon, 2018-10-29 at 11:16 +0800, Rick Chen wrote: > > Auer, Lukas 於 2018年10月27日 週六 > > 上午12:32寫道： > > > > > > Hi Rick, > > > > > > On Mon, 2018-10-22 at 16:16 +0800, Andes wrote: > > > > From: Rick Chen > > > > > > > > AndeStar V5

Re: [U-Boot] [PATCH] riscv: cache: Implement i/dcache [status, enable, disable]

2018-10-29 Thread Auer, Lukas
Hi Rick, On Mon, 2018-10-29 at 11:16 +0800, Rick Chen wrote: > Auer, Lukas 於 2018年10月27日 週六 > 上午12:32寫道： > > > > Hi Rick, > > > > On Mon, 2018-10-22 at 16:16 +0800, Andes wrote: > > > From: Rick Chen > > > > > > AndeStar V5 provide mcache_ctl register which can configure > > > I/D cache as

Re: [U-Boot] [PATCH] riscv: cache: Implement i/dcache [status, enable, disable]

2018-10-28 Thread Rick Chen
Auer, Lukas 於 2018年10月27日 週六 上午12:32寫道： > > Hi Rick, > > On Mon, 2018-10-22 at 16:16 +0800, Andes wrote: > > From: Rick Chen > > > > AndeStar V5 provide mcache_ctl register which can configure > > I/D cache as enabled or disabled. > > > > This CSR will be encapsulated by CONFIG_NDS_V5. > > If

Re: [U-Boot] [PATCH] riscv: cache: Implement i/dcache [status, enable, disable]

2018-10-26 Thread Auer, Lukas
Hi Rick, On Mon, 2018-10-22 at 16:16 +0800, Andes wrote: > From: Rick Chen > > AndeStar V5 provide mcache_ctl register which can configure > I/D cache as enabled or disabled. > > This CSR will be encapsulated by CONFIG_NDS_V5. > If you want to configure cache on AndeStar V5 > AE350 platform.