Re: [U-Boot] [PATCH 1/5] riscv: dts: Add hifive-unleashed-a00 dts from Linux
Hi Jagan, On Wed, 2019-10-02 at 15:57 +0530, Jagan Teki wrote: > On Mon, Sep 30, 2019 at 3:35 PM Bin Meng wrote: > > Hi Jagan, > > > > On Sun, Sep 29, 2019 at 3:42 PM Jagan Teki > > wrote: > > > Sync the hifive-unleashed-a00 dts from Linux with > > > below commit details: > > > commit 11ae2d892139a1086f257188d457ddcb71ab5257 > > > > The latest commit should be: > > > > commit c81007116bd23e9e2103c267184dc38d3acc1099 > > Author: Bin Meng > > Date: Thu Sep 5 05:45:53 2019 -0700 > > > > riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes > > > > Could you use the latest one? > > Syncing these commits other than the patch used one seems not working. > SBI is failing to load u-boot-dtb.bin. I think this would some sort of > cpu nodes changes on commits after > riscv: dts: fu540-c000: drop "timebase-frequency" I just tried it with the device tree from the commit Bin referred to and did not have any problems starting U-Boot. Are you perhaps only missing chosen/stdout-path? Thanks, Lukas ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] riscv: dts: Add hifive-unleashed-a00 dts from Linux
Hi Jagan,
On Sun, 2019-09-29 at 13:12 +0530, Jagan Teki wrote:
> Sync the hifive-unleashed-a00 dts from Linux with
> below commit details:
> commit 11ae2d892139a1086f257188d457ddcb71ab5257
> Author: Paul Walmsley
> Date: Thu Jul 25 13:41:31 2019 -0700
>
> riscv: dts: fu540-c000: drop "timebase-frequency"
>
> Idea is to periodically sync the dts from Linux instead of
> tweeking internal changes one after another, so better not
> add any intermediate changes in between. This would help to
> maintain the dts files easy and meaningful since we are
> reusing devicetree files from Linux.
>
> Signed-off-by: Jagan Teki
> ---
> arch/riscv/dts/Makefile | 1 +
> arch/riscv/dts/fu540-c000.dtsi | 235
> arch/riscv/dts/hifive-unleashed-a00.dts | 88 +
> 3 files changed, 324 insertions(+)
> create mode 100644 arch/riscv/dts/fu540-c000.dtsi
> create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts
>
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> index f9cd606a9a..4f30e6936f 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0+
>
> dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> +dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
>
> targets += $(dtb-y)
>
> diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi
> new file mode 100644
> index 00..42b5ec2231
> --- /dev/null
> +++ b/arch/riscv/dts/fu540-c000.dtsi
> @@ -0,0 +1,235 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2018-2019 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "sifive,fu540-c000", "sifive,fu540";
> +
> + aliases {
> + serial0 =
> + serial1 =
> + };
> +
> + chosen {
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu0: cpu@0 {
> + compatible = "sifive,e51", "sifive,rocket0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + reg = <0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu1: cpu@1 {
> + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <1>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu2: cpu@2 {
> + clock-frequency = <0>;
> + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <2>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu3: cpu@3 {
> + clock-frequency = <0>;
> +
Re: [U-Boot] [PATCH 1/5] riscv: dts: Add hifive-unleashed-a00 dts from Linux
On Mon, Sep 30, 2019 at 3:35 PM Bin Meng wrote: > > Hi Jagan, > > On Sun, Sep 29, 2019 at 3:42 PM Jagan Teki wrote: > > > > Sync the hifive-unleashed-a00 dts from Linux with > > below commit details: > > commit 11ae2d892139a1086f257188d457ddcb71ab5257 > > The latest commit should be: > > commit c81007116bd23e9e2103c267184dc38d3acc1099 > Author: Bin Meng > Date: Thu Sep 5 05:45:53 2019 -0700 > > riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes > > Could you use the latest one? Syncing these commits other than the patch used one seems not working. SBI is failing to load u-boot-dtb.bin. I think this would some sort of cpu nodes changes on commits after riscv: dts: fu540-c000: drop "timebase-frequency" ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] riscv: dts: Add hifive-unleashed-a00 dts from Linux
On Mon, Sep 30, 2019 at 3:35 PM Bin Meng wrote: > > Hi Jagan, > > On Sun, Sep 29, 2019 at 3:42 PM Jagan Teki wrote: > > > > Sync the hifive-unleashed-a00 dts from Linux with > > below commit details: > > commit 11ae2d892139a1086f257188d457ddcb71ab5257 > > The latest commit should be: > > commit c81007116bd23e9e2103c267184dc38d3acc1099 > Author: Bin Meng > Date: Thu Sep 5 05:45:53 2019 -0700 > > riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes > > Could you use the latest one? Yes, will use this. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] riscv: dts: Add hifive-unleashed-a00 dts from Linux
Hi Jagan, On Sun, Sep 29, 2019 at 3:42 PM Jagan Teki wrote: > > Sync the hifive-unleashed-a00 dts from Linux with > below commit details: > commit 11ae2d892139a1086f257188d457ddcb71ab5257 The latest commit should be: commit c81007116bd23e9e2103c267184dc38d3acc1099 Author: Bin Meng Date: Thu Sep 5 05:45:53 2019 -0700 riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes Could you use the latest one? > Author: Paul Walmsley > Date: Thu Jul 25 13:41:31 2019 -0700 > > riscv: dts: fu540-c000: drop "timebase-frequency" > > Idea is to periodically sync the dts from Linux instead of > tweeking internal changes one after another, so better not typo, tweaking > add any intermediate changes in between. This would help to > maintain the dts files easy and meaningful since we are > reusing devicetree files from Linux. nits: device tree > > Signed-off-by: Jagan Teki > --- > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/fu540-c000.dtsi | 235 > arch/riscv/dts/hifive-unleashed-a00.dts | 88 + > 3 files changed, 324 insertions(+) > create mode 100644 arch/riscv/dts/fu540-c000.dtsi > create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts > Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
