On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <s...@chromium.org> wrote: > While queensbay is the first chip with these settings, others will want to > use them too. Make them common. > > Signed-off-by: Simon Glass <s...@chromium.org> > --- > > arch/x86/Kconfig | 38 ++++++++++++++++++++++++++++++++++++++ > arch/x86/cpu/queensbay/Kconfig | 38 -------------------------------------- > 2 files changed, 38 insertions(+), 38 deletions(-) > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index 1523c91..73a7392 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -344,6 +344,44 @@ config TSC_FREQ_IN_MHZ > help > The running frequency in MHz of Time-Stamp Counter (TSC). > > +config HAVE_FSP > + bool "Add an Firmware Support Package binary" > + help > + Select this option to add an Firmware Support Package binary to > + the resulting U-Boot image. It is a binary blob which U-Boot uses > + to set up SDRAM and other chipset specific initialization. > + > + Note: Without this binary U-Boot will not be able to set up its > + SDRAM so will not boot. > + > +config FSP_FILE > + string "Firmware Support Package binary filename" > + depends on HAVE_FSP > + default "fsp.bin" > + help > + The filename of the file to use as Firmware Support Package binary > + in the board directory. > + > +config FSP_ADDR > + hex "Firmware Support Package binary location" > + depends on HAVE_FSP > + default 0xfffc0000 > + help > + FSP is not Position Independent Code (PIC) and the whole FSP has to > + be rebased if it is placed at a location which is different from the > + perferred base address specified during the FSP build. Use Intel's > + Binary Configuration Tool (BCT) to do the rebase. > + > + The default base address of 0xfffc0000 indicates that the binary > must > + be located at offset 0xc0000 from the beginning of a 1MB flash > device. > + > +config FSP_TEMP_RAM_ADDR > + hex > + default 0x2000000 > + help > + Stack top address which is used in FspInit after DRAM is ready and > + CAR is disabled. > + > source "arch/x86/cpu/coreboot/Kconfig" > > source "arch/x86/cpu/ivybridge/Kconfig" > diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig > index f6b5201..397e599 100644 > --- a/arch/x86/cpu/queensbay/Kconfig > +++ b/arch/x86/cpu/queensbay/Kconfig > @@ -11,44 +11,6 @@ config INTEL_QUEENSBAY > > if INTEL_QUEENSBAY > > -config HAVE_FSP > - bool "Add an Firmware Support Package binary" > - help > - Select this option to add an Firmware Support Package binary to > - the resulting U-Boot image. It is a binary blob which U-Boot uses > - to set up SDRAM and other chipset specific initialization. > - > - Note: Without this binary U-Boot will not be able to set up its > - SDRAM so will not boot. > - > -config FSP_FILE > - string "Firmware Support Package binary filename" > - depends on HAVE_FSP > - default "fsp.bin" > - help > - The filename of the file to use as Firmware Support Package binary > - in the board directory. > - > -config FSP_ADDR > - hex "Firmware Support Package binary location" > - depends on HAVE_FSP > - default 0xfffc0000 > - help > - FSP is not Position Independent Code (PIC) and the whole FSP has to > - be rebased if it is placed at a location which is different from the > - perferred base address specified during the FSP build. Use Intel's > - Binary Configuration Tool (BCT) to do the rebase. > - > - The default base address of 0xfffc0000 indicates that the binary > must > - be located at offset 0xc0000 from the beginning of a 1MB flash > device. > - > -config FSP_TEMP_RAM_ADDR > - hex > - default 0x2000000 > - help > - Stack top address which is used in FspInit after DRAM is ready and > - CAR is disabled. > - > config HAVE_CMC > bool "Add a Chipset Micro Code state machine binary" > help > --
Reviewed-by: Bin Meng <bmeng...@gmail.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot