On Sun, Sep 18, 2016 at 01:45:16PM -0600, Simon Glass wrote: > There is no need for this to be in the BSS region. By moving it we can delay > use of BSS in SPL. This is useful for machines where the BSS region is not > in writeable space. On 64-bit x86, SPL runs from SPI flash and it is easier > to eliminate BSS use than link SPL to run with BSS at a particular > cache-as-RAM (CAR) address. > > Signed-off-by: Simon Glass <s...@chromium.org>
Reviewed-by: Tom Rini <tr...@konsulko.com> -- Tom
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