Hi,
On 03/16/2014 02:53 PM, Hans de Goede wrote:
Woops I forgot to add a commit msg here, I've jut fixed this locally:
Based linux-sunxi#sunxi commit d854c4de2f57 arm: Handle .gnu.hash section
in
ldscripts vs v2014.01.
As well as the following signed-off-by the sunxi branch shows commits to
the new sun4i dram bits by:
Berg Xing bergx...@allwinnertech.com
Tom Cubie tangli...@allwinnertech.com
Signed-off-by: Henrik Nordstrom hen...@henriknordstrom.net
Signed-off-by: Stefan Roese s...@denx.de
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
Regards,
Hans
---
arch/arm/cpu/armv7/sunxi/board.c| 2 +-
arch/arm/cpu/armv7/sunxi/clock.c| 2 +
arch/arm/cpu/armv7/sunxi/cpu_info.c | 7 ++
arch/arm/cpu/armv7/sunxi/dram.c | 129
board/sunxi/Makefile| 3 +-
board/sunxi/dram_a10_olinuxino_l.c | 31 +
boards.cfg | 1 +
drivers/mmc/sunxi_mmc.c | 10 +++
include/configs/sun4i.h | 40 +++
9 files changed, 223 insertions(+), 2 deletions(-)
create mode 100644 board/sunxi/dram_a10_olinuxino_l.c
create mode 100644 include/configs/sun4i.h
diff --git a/arch/arm/cpu/armv7/sunxi/board.c
b/arch/arm/cpu/armv7/sunxi/board.c
index 2668d52..2225e31 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -82,7 +82,7 @@ void reset_cpu(ulong addr)
/* do some early init */
void s_init(void)
{
-#if !defined CONFIG_SPL_BUILD
+#if !defined CONFIG_SPL_BUILD defined CONFIG_SUN7I
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
mrc p15, 0, r0, c1, c0, 1\n
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c
b/arch/arm/cpu/armv7/sunxi/clock.c
index e3abaf0..f685dda 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -43,8 +43,10 @@ static void clock_init_safe(void)
sdelay(200);
writel(AXI_DIV_1 0 | AHB_DIV_2 4 | APB0_DIV_1 8 |
CPU_CLK_SRC_PLL1 16, ccm-cpu_ahb_apb0_cfg);
+#ifdef CONFIG_SUN7I
writel(0x1 6 | readl(ccm-ahb_gate0), ccm-ahb_gate0);
writel(0x1 31 | readl(ccm-pll6_cfg), ccm-pll6_cfg);
+#endif
}
#endif
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c
b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 14093dd..31c9f96 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -29,7 +29,14 @@
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
+#ifdef CONFIG_SUN4I
+ puts(CPU: Allwinner A10 (SUN4I)\n);
+#elif defined CONFIG_SUN7I
puts(CPU: Allwinner A20 (SUN7I)\n);
+#else
+#warning Please update cpu_info.c with correct CPU information
+ puts(CPU: SUNXI Family\n);
+#endif
return 0;
}
#endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index c34322d..08db987 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -49,6 +49,21 @@ static void mctl_ddr3_reset(void)
struct sunxi_dram_reg *dram =
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+#ifdef CONFIG_SUN4I
+ struct sunxi_timer_reg *timer =
+ (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+ u32 reg_val;
+
+ writel(0, timer-cpu_cfg);
+ reg_val = readl(timer-cpu_cfg);
+
+ if ((reg_val CPU_CFG_CHIP_VER_MASK) !=
+ CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
+ setbits_le32(dram-mcr, DRAM_MCR_RESET);
+ udelay(2);
+ clrbits_le32(dram-mcr, DRAM_MCR_RESET);
+ } else
+#endif
{
clrbits_le32(dram-mcr, DRAM_MCR_RESET);
udelay(2);
@@ -60,7 +75,11 @@ static void mctl_set_drive(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+#ifdef CONFIG_SUN7I
clrsetbits_le32(dram-mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 28),
+#else
+ clrsetbits_le32(dram-mcr, DRAM_MCR_MODE_NORM(0x3),
+#endif
DRAM_MCR_MODE_EN(0x3) |
0xffc);
}
@@ -112,7 +131,11 @@ static void mctl_enable_dllx(u32 phase)
n = DRAM_DCR_NR_DLLCR_16BIT;
for (i = 1; i n; i++) {
+#ifdef CONFIG_SUN7I
clrsetbits_le32(dram-dllcr[i], 0xf 14,
+#else
+ clrsetbits_le32(dram-dllcr[i], 0x4 14,
+#endif
(phase 0xf) 14);
clrsetbits_le32(dram-dllcr[i], DRAM_DLLCR_NRESET,
DRAM_DLLCR_DISABLE);
@@ -132,6 +155,17 @@ static void mctl_enable_dllx(u32 phase)
}
static u32 hpcr_value[32] = {
+#ifdef CONFIG_SUN4I
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0x0301, 0x0301, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0x1031, 0x1031, 0x0735, 0x1035,
+ 0x1035,
