Hi Jagan,
On Sat, Sep 17, 2016 at 02:18:40AM +0530, Jagan Teki wrote:
>Add i.MX6DL dtsi support from Linux.
Better including the latest linux commit number.
Regards,
Peng.
>
>Cc: Peng Fan <peng....@nxp.com>
>Cc: Stefano Babic <sba...@denx.de>
>Cc: Fabio Estevam <fabio.este...@nxp.com>
>Cc: Matteo Lisi <matteo.l...@engicam.com>
>Cc: Michael Trimarchi <mich...@amarulasolutions.com>
>Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
>---
> arch/arm/dts/imx6dl.dtsi | 133 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 133 insertions(+)
> create mode 100644 arch/arm/dts/imx6dl.dtsi
>
>diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
>new file mode 100644
>index 0000000..9a4c22c
>--- /dev/null
>+++ b/arch/arm/dts/imx6dl.dtsi
>@@ -0,0 +1,133 @@
>+
>+/*
>+ * Copyright 2013 Freescale Semiconductor, Inc.
>+ *
>+ * This program is free software; you can redistribute it and/or modify
>+ * it under the terms of the GNU General Public License version 2 as
>+ * published by the Free Software Foundation.
>+ *
>+ */
>+
>+#include <dt-bindings/interrupt-controller/irq.h>
>+#include "imx6dl-pinfunc.h"
>+#include "imx6qdl.dtsi"
>+
>+/ {
>+ aliases {
>+ i2c3 = &i2c4;
>+ };
>+
>+ cpus {
>+ #address-cells = <1>;
>+ #size-cells = <0>;
>+
>+ cpu@0 {
>+ compatible = "arm,cortex-a9";
>+ device_type = "cpu";
>+ reg = <0>;
>+ next-level-cache = <&L2>;
>+ operating-points = <
>+ /* kHz uV */
>+ 996000 1250000
>+ 792000 1175000
>+ 396000 1150000
>+ >;
>+ fsl,soc-operating-points = <
>+ /* ARM kHz SOC-PU uV */
>+ 996000 1175000
>+ 792000 1175000
>+ 396000 1175000
>+ >;
>+ clock-latency = <61036>; /* two CLK32 periods */
>+ clocks = <&clks IMX6QDL_CLK_ARM>,
>+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
>+ <&clks IMX6QDL_CLK_STEP>,
>+ <&clks IMX6QDL_CLK_PLL1_SW>,
>+ <&clks IMX6QDL_CLK_PLL1_SYS>;
>+ clock-names = "arm", "pll2_pfd2_396m", "step",
>+ "pll1_sw", "pll1_sys";
>+ arm-supply = <®_arm>;
>+ pu-supply = <®_pu>;
>+ soc-supply = <®_soc>;
>+ };
>+
>+ cpu@1 {
>+ compatible = "arm,cortex-a9";
>+ device_type = "cpu";
>+ reg = <1>;
>+ next-level-cache = <&L2>;
>+ };
>+ };
>+
>+ soc {
>+ ocram: sram@00900000 {
>+ compatible = "mmio-sram";
>+ reg = <0x00900000 0x20000>;
>+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
>+ };
>+
>+ aips1: aips-bus@02000000 {
>+ iomuxc: iomuxc@020e0000 {
>+ compatible = "fsl,imx6dl-iomuxc";
>+ };
>+
>+ pxp: pxp@020f0000 {
>+ reg = <0x020f0000 0x4000>;
>+ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
>+ };
>+
>+ epdc: epdc@020f4000 {
>+ reg = <0x020f4000 0x4000>;
>+ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
>+ };
>+
>+ lcdif: lcdif@020f8000 {
>+ reg = <0x020f8000 0x4000>;
>+ interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
>+ };
>+ };
>+
>+ aips2: aips-bus@02100000 {
>+ i2c4: i2c@021f8000 {
>+ #address-cells = <1>;
>+ #size-cells = <0>;
>+ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
>+ reg = <0x021f8000 0x4000>;
>+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
>+ clocks = <&clks IMX6DL_CLK_I2C4>;
>+ status = "disabled";
>+ };
>+ };
>+ };
>+
>+ display-subsystem {
>+ compatible = "fsl,imx-display-subsystem";
>+ ports = <&ipu1_di0>, <&ipu1_di1>;
>+ };
>+
>+ gpu-subsystem {
>+ compatible = "fsl,imx-gpu-subsystem";
>+ cores = <&gpu_2d>, <&gpu_3d>;
>+ };
>+};
>+
>+&gpt {
>+ compatible = "fsl,imx6dl-gpt";
>+};
>+
>+&hdmi {
>+ compatible = "fsl,imx6dl-hdmi";
>+};
>+
>+&ldb {
>+ clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks
>IMX6QDL_CLK_LDB_DI1_SEL>,
>+ <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks
>IMX6QDL_CLK_IPU1_DI1_SEL>,
>+ <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
>+ clock-names = "di0_pll", "di1_pll",
>+ "di0_sel", "di1_sel",
>+ "di0", "di1";
>+};
>+
>+&vpu {
>+ compatible = "fsl,imx6dl-vpu", "cnm,coda960";
>+};
>--
>2.7.4
>
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