Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver
On Wed, May 2, 2018 at 2:49 PM, Siva Durga Prasad Paladugu
wrote:
> Hi,
>
>> -Original Message-
>> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
>> Sent: Wednesday, April 25, 2018 10:47 AM
>> To: Siva Durga Prasad Paladugu
>> Cc: U-Boot-Denx
>> Subject: Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for
>> ZynqMP qspi driver
[snip]
>> >>
>> >> > +
>> >> > + plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
>> >> > +
>> >> > ZYNQMP_GQSPI_REG_OFFSET);
>> >> > + plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
>> >> > + (devfdt_get_addr(bus) +
>> >> > + ZYNQMP_GQSPI_DMA_REG_OFFSET);
>> >> > +
>> >> > + ret = clk_get_by_index(bus, 0, &clk);
>> >> > + if (ret < 0) {
>> >> > + dev_err(dev, "failed to get clock\n");
>> >> > + return ret;
>> >> > + }
>> >> > +
>> >> > + clock = clk_get_rate(&clk);
>> >> > + if (IS_ERR_VALUE(clock)) {
>> >> > + dev_err(dev, "failed to get rate\n");
>> >> > + return clock;
>> >> > + }
>> >> > + debug("%s: CLK %ld\n", __func__, clock);
>> >> > +
>> >> > + ret = clk_enable(&clk);
>> >> > + if (ret && ret != -ENOSYS) {
>> >> > + dev_err(dev, "failed to enable clock\n");
>> >> > + return ret;
>> >> > + }
>> >> > +
>> >> > + value = dev_read_u32_default(bus, "spi-rx-bus-width", 1);
>> >> > + switch (value) {
>> >> > + case 1:
>> >> > + break;
>> >> > + case 2:
>> >> > + mode |= SPI_RX_DUAL;
>> >> > + break;
>> >> > + case 4:
>> >> > + mode |= SPI_RX_QUAD;
>> >> > + break;
>> >> > + default:
>> >> > + printf("Invalid spi-rx-bus-width %d\n", value);
>> >> > + break;
>> >> > + }
>> >> > +
>> >> > + value = dev_read_u32_default(bus, "spi-tx-bus-width", 1);
>> >> > + switch (value) {
>> >> > + case 1:
>> >> > + break;
>> >> > + case 2:
>> >> > + mode |= SPI_TX_DUAL;
>> >> > + break;
>> >> > + case 4:
>> >> > + mode |= SPI_TX_QUAD;
>> >> > + break;
>> >> > + default:
>> >> > + printf("Invalid spi-tx-bus-width %d\n", value);
>> >> > + break;
>> >> > + }
>> >> > +
>> >> > + plat->tx_rx_mode = mode;
>> >> > +
>> >> > + plat->frequency = clock;
>> >> > + plat->speed_hz = plat->frequency;
>> >>
>> >> why we need this? all these are generic stuff which is available at
>> >> spi- uclass.c
>> >
>> > Somehow I am not able to get these from spi-uclass.c , the routine which
>> reads all these info from dt in spi-uclass.c is never getting invoked in my
>> flow.
>> > I checked other driver as well,. Do you have an idea on why is it so?
>>
>> All these attributes are from platdata which were initialized by spi-uclass.c
>> so if you need any of these we can get the dm_spi_slave_platdata from
>> your driver using dev_get_parent_platdata() function.
>
> Looks like you didn’t get my point, in my flow the routine
> spi_slave_ofdata_to_platdata() in spi-uclass.c is
> not getting invoked at all that’s why I am not getting this data from
> spi-uclass.c. do you have an idea on
> what could be the issue that spi_slave_ofdata_to_platdata() is not getting
> invoked.
> I will anyway debug it but, if you already encountered this and aware of any
> reason for this , please let me know, that really helps me.
Fix the rest and keep this as it is we will discuss on next version.
Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver
Hi, > -Original Message- > From: Jagan Teki [mailto:ja...@amarulasolutions.com] > Sent: Wednesday, April 25, 2018 10:47 AM > To: Siva Durga Prasad Paladugu > Cc: U-Boot-Denx > Subject: Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for > ZynqMP qspi driver > > On Wed, Feb 7, 2018 at 3:40 PM, Siva Durga Prasad Paladugu > wrote: > > Hi Jagan, > > > > > >> -Original Message- > >> From: Jagan Teki [mailto:ja...@amarulasolutions.com] > >> Sent: Tuesday, January 23, 2018 10:41 PM > >> To: Siva Durga Prasad Paladugu > >> Cc: U-Boot-Denx ; Siva Durga Prasad Paladugu > >> > >> Subject: Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support > >> for ZynqMP qspi driver > >> > >> On Thu, Jan 4, 2018 at 1:07 PM, Siva Durga Prasad Paladugu > >> wrote: > >> > This patch adds qspi driver support for ZynqMP SoC. This driver is > >> > responsible for communicating with qspi flash devices. > >> > > >> > Signed-off-by: Siva Durga Prasad Paladugu > >> > --- > >> > Changes from v1: > >> > - Rebased on top of latest master > >> > - Moved macro definitions to .h file as per comment > >> > - Fixed magic values with macros as per comment > >> > --- > >> > arch/arm/cpu/armv8/zynqmp/Kconfig | 7 + > >> > arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h | 154 ++ > >> > drivers/spi/Makefile | 1 + > >> > drivers/spi/zynqmp_qspi.c | 678 > >> + > >> > >> Was this gqspi like linux spi-zynqmp-gqspi.c or different? > > Yes. > > then try to use similar naming conventions in macros, or in function names > as well. > > > > >> > >> > 4 files changed, 840 insertions(+) create mode 100644 > >> > arch/arm/include/asm/arch- > >> zynqmp/zynqmp_qspi.h > >> > create mode 100644 drivers/spi/zynqmp_qspi.c > >> > > >> > diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig > >> > b/arch/arm/cpu/armv8/zynqmp/Kconfig > >> > index 3f922b4..2fe4f71 100644 > >> > --- a/arch/arm/cpu/armv8/zynqmp/Kconfig > >> > +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig > >> > @@ -65,6 +65,13 @@ config PMUFW_INIT_FILE > >> > Include external PMUFW (Platform Management Unit FirmWare) > to > >> > a Xilinx bootable image (boot.bin). > >> > > >> > +config ZYNQMP_QSPI > >> > + bool "Configure ZynqMP QSPI" > >> > + select DM_SPI > >> > + help > >> > + This option is used to enable ZynqMP QSPI controller driver > which > >> > + is used to communicate with qspi flash devices. > >> > >> I've commented this before, what is the reason for adding spi kconfig > >> entry in arch area instead of drivers/spi? > > > > I might have missed it, Will move to drivers/spi > >> > >> > + > >> > config ZYNQMP_USB > >> > bool "Configure ZynqMP USB" > >> > > >> > diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > >> > b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > >> > new file mode 100644 > >> > index 000..5e2926e > >> > --- /dev/null > >> > +++ b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > >> > @@ -0,0 +1,154 @@ > >> > +/* > >> > + * (C) Copyright 2014 - 2015 Xilinx > >> > + * > >> > + * Xilinx ZynqMP Quad-SPI(QSPI) controller driver (master mode > >> > +only) > >> > + * > >> > + * SPDX-License-Identifier:GPL-2.0+ > >> > + */ > >> > + > >> > +#ifndef _ASM_ARCH_ZYNQMP_QSPI_H_ > >> > +#define _ASM_ARCH_ZYNQMP_QSPI_H_ > >> > + > >> > +#define ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK BIT(29) > >> > +#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASK(3 << 30) > >> > +#define ZYNQMP_QSPI_CONFIG_DMA_MODE(2 << 30) > >> > +#define ZYNQMP_QSPI_CONFIG_CPHA_MASK BIT(2) > >> > +#define ZYNQMP_QSPI_CONFIG_CPOL_MASK BIT(1) > >> > + > >> > +/* QSPI MIO's count for different connection topologies */ > >> > +#define ZYNQMP_QSPI_MIO_NUM_QSPI0 6 > >> > +#define ZYNQMP_QSPI_MIO_NUM_QSPI1 5 >
Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver
On Wed, Feb 7, 2018 at 3:40 PM, Siva Durga Prasad Paladugu wrote: > Hi Jagan, > > >> -Original Message- >> From: Jagan Teki [mailto:ja...@amarulasolutions.com] >> Sent: Tuesday, January 23, 2018 10:41 PM >> To: Siva Durga Prasad Paladugu >> Cc: U-Boot-Denx ; Siva Durga Prasad Paladugu >> >> Subject: Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for >> ZynqMP qspi driver >> >> On Thu, Jan 4, 2018 at 1:07 PM, Siva Durga Prasad Paladugu >> wrote: >> > This patch adds qspi driver support for ZynqMP SoC. This driver is >> > responsible for communicating with qspi flash devices. >> > >> > Signed-off-by: Siva Durga Prasad Paladugu >> > --- >> > Changes from v1: >> > - Rebased on top of latest master >> > - Moved macro definitions to .h file as per comment >> > - Fixed magic values with macros as per comment >> > --- >> > arch/arm/cpu/armv8/zynqmp/Kconfig | 7 + >> > arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h | 154 ++ >> > drivers/spi/Makefile | 1 + >> > drivers/spi/zynqmp_qspi.c | 678 >> + >> >> Was this gqspi like linux spi-zynqmp-gqspi.c or different? > Yes. then try to use similar naming conventions in macros, or in function names as well. > >> >> > 4 files changed, 840 insertions(+) >> > create mode 100644 arch/arm/include/asm/arch- >> zynqmp/zynqmp_qspi.h >> > create mode 100644 drivers/spi/zynqmp_qspi.c >> > >> > diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig >> > b/arch/arm/cpu/armv8/zynqmp/Kconfig >> > index 3f922b4..2fe4f71 100644 >> > --- a/arch/arm/cpu/armv8/zynqmp/Kconfig >> > +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig >> > @@ -65,6 +65,13 @@ config PMUFW_INIT_FILE >> > Include external PMUFW (Platform Management Unit FirmWare) to >> > a Xilinx bootable image (boot.bin). >> > >> > +config ZYNQMP_QSPI >> > + bool "Configure ZynqMP QSPI" >> > + select DM_SPI >> > + help >> > + This option is used to enable ZynqMP QSPI controller driver which >> > + is used to communicate with qspi flash devices. >> >> I've commented this before, what is the reason for adding spi kconfig entry >> in arch area instead of drivers/spi? > > I might have missed it, Will move to drivers/spi >> >> > + >> > config ZYNQMP_USB >> > bool "Configure ZynqMP USB" >> > >> > diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h >> > b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h >> > new file mode 100644 >> > index 000..5e2926e >> > --- /dev/null >> > +++ b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h >> > @@ -0,0 +1,154 @@ >> > +/* >> > + * (C) Copyright 2014 - 2015 Xilinx >> > + * >> > + * Xilinx ZynqMP Quad-SPI(QSPI) controller driver (master mode only) >> > + * >> > + * SPDX-License-Identifier:GPL-2.0+ >> > + */ >> > + >> > +#ifndef _ASM_ARCH_ZYNQMP_QSPI_H_ >> > +#define _ASM_ARCH_ZYNQMP_QSPI_H_ >> > + >> > +#define ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK BIT(29) >> > +#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASK(3 << 30) >> > +#define ZYNQMP_QSPI_CONFIG_DMA_MODE(2 << 30) >> > +#define ZYNQMP_QSPI_CONFIG_CPHA_MASK BIT(2) >> > +#define ZYNQMP_QSPI_CONFIG_CPOL_MASK BIT(1) >> > + >> > +/* QSPI MIO's count for different connection topologies */ >> > +#define ZYNQMP_QSPI_MIO_NUM_QSPI0 6 >> > +#define ZYNQMP_QSPI_MIO_NUM_QSPI1 5 >> > +#define ZYNQMP_QSPI_MIO_NUM_QSPI1_CS 1 >> > + >> > +/* >> > + * QSPI Interrupt Registers bit Masks >> > + * >> > + * All the four interrupt registers (Status/Mask/Enable/Disable) have >> > +the same >> > + * bit definitions. >> > + */ >> > +#define ZYNQMP_QSPI_IXR_TXNFULL_MASK 0x0004 /* QSPI TX >> FIFO Overflow */ >> > +#define ZYNQMP_QSPI_IXR_TXFULL_MASK0x0008 /* QSPI TX >> FIFO is full */ >> > +#define ZYNQMP_QSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX >> FIFO Not Empty */ >> > +#define ZYNQMP_QSPI_IXR_GFEMTY_MASK0x0080 /* QSPI >> Generic FIFO Empty */ >> > +#define ZYNQMP_QSPI_IXR_ALL_MASK >> (ZYNQMP_QSPI_IXR_TXNFULL_MASK | \ >
Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver
Hi Siva, I wasn't able to find it on the Xilinx github. Is it in that tree already? Thanks, Liam On Thu, 12 Apr 2018 at 07:18 Siva Durga Prasad Paladugu wrote: > Hi Liam, > > > > We already have a patch for IO mode that we just verified internally. We > got it for our tree from NGC guy John Moon. I will be sending that patch > soon may be with v3 which I am planning to send once I got response from > Jagan on my v2 queries. > > > > Regards, > > Siva > > > > *From:* Liam Beguin [mailto:liambeg...@gmail.com] > *Sent:* Tuesday, April 10, 2018 8:56 PM > *To:* Siva Durga Prasad Paladugu > *Cc:* Jagan Teki ; U-Boot-Denx < > u-boot@lists.denx.de>; Michal Simek > > > *Subject:* Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for > ZynqMP qspi driver > > > > Hi Siva, > > > > I've been working on a patch to add support for io-mode [1]. > > It's based on xilinx/master which is closer to v1 (no include file). > > I haven't had much time to test it further but I can load a bitstream > > from a ubifs partition with it. > > Let me know if you have comments. > > > > On Tue, 10 Apr 2018 at 02:27 Siva Durga Prasad Paladugu < > siva...@xilinx.com> wrote: > > H Jagan, > > Any further comments on this. I am waiting for your reply on some of my > replies to your comment. > > Thanks, > Siva > > > > Thanks, > > Liam > > > > [1] https://github.com/Liambeguin/u-boot/tree/io-mode > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver
Hi Liam, We already have a patch for IO mode that we just verified internally. We got it for our tree from NGC guy John Moon. I will be sending that patch soon may be with v3 which I am planning to send once I got response from Jagan on my v2 queries. Regards, Siva From: Liam Beguin [mailto:liambeg...@gmail.com] Sent: Tuesday, April 10, 2018 8:56 PM To: Siva Durga Prasad Paladugu Cc: Jagan Teki ; U-Boot-Denx ; Michal Simek Subject: Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver Hi Siva, I've been working on a patch to add support for io-mode [1]. It's based on xilinx/master which is closer to v1 (no include file). I haven't had much time to test it further but I can load a bitstream from a ubifs partition with it. Let me know if you have comments. On Tue, 10 Apr 2018 at 02:27 Siva Durga Prasad Paladugu mailto:siva...@xilinx.com>> wrote: H Jagan, Any further comments on this. I am waiting for your reply on some of my replies to your comment. Thanks, Siva Thanks, Liam [1] https://github.com/Liambeguin/u-boot/tree/io-mode ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver
Hi Siva, I've been working on a patch to add support for io-mode [1]. It's based on xilinx/master which is closer to v1 (no include file). I haven't had much time to test it further but I can load a bitstream from a ubifs partition with it. Let me know if you have comments. On Tue, 10 Apr 2018 at 02:27 Siva Durga Prasad Paladugu wrote: > H Jagan, > > Any further comments on this. I am waiting for your reply on some of my > replies to your comment. > > Thanks, > Siva > > Thanks, Liam [1] https://github.com/Liambeguin/u-boot/tree/io-mode ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver
H Jagan, Any further comments on this. I am waiting for your reply on some of my replies to your comment. Thanks, Siva > -Original Message- > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Siva > Durga Prasad Paladugu > Sent: Wednesday, February 07, 2018 3:40 PM > To: Jagan Teki > Cc: U-Boot-Denx > Subject: Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for > ZynqMP qspi driver > > [This sender failed our fraud detection checks and may not be who they > appear to be. Learn about spoofing at http://aka.ms/LearnAboutSpoofing] > > Hi Jagan, > > > > -Original Message- > > From: Jagan Teki [mailto:ja...@amarulasolutions.com] > > Sent: Tuesday, January 23, 2018 10:41 PM > > To: Siva Durga Prasad Paladugu > > Cc: U-Boot-Denx ; Siva Durga Prasad Paladugu > > > > Subject: Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for > > ZynqMP qspi driver > > > > On Thu, Jan 4, 2018 at 1:07 PM, Siva Durga Prasad Paladugu > > wrote: > > > This patch adds qspi driver support for ZynqMP SoC. This driver is > > > responsible for communicating with qspi flash devices. > > > > > > Signed-off-by: Siva Durga Prasad Paladugu > > > --- > > > Changes from v1: > > > - Rebased on top of latest master > > > - Moved macro definitions to .h file as per comment > > > - Fixed magic values with macros as per comment > > > --- > > > arch/arm/cpu/armv8/zynqmp/Kconfig | 7 + > > > arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h | 154 ++ > > > drivers/spi/Makefile | 1 + > > > drivers/spi/zynqmp_qspi.c | 678 > > + > > > > Was this gqspi like linux spi-zynqmp-gqspi.c or different? > Yes. > > > > > > 4 files changed, 840 insertions(+) > > > create mode 100644 arch/arm/include/asm/arch- > > zynqmp/zynqmp_qspi.h > > > create mode 100644 drivers/spi/zynqmp_qspi.c > > > > > > diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig > > > b/arch/arm/cpu/armv8/zynqmp/Kconfig > > > index 3f922b4..2fe4f71 100644 > > > --- a/arch/arm/cpu/armv8/zynqmp/Kconfig > > > +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig > > > @@ -65,6 +65,13 @@ config PMUFW_INIT_FILE > > > Include external PMUFW (Platform Management Unit FirmWare) > to > > > a Xilinx bootable image (boot.bin). > > > > > > +config ZYNQMP_QSPI > > > + bool "Configure ZynqMP QSPI" > > > + select DM_SPI > > > + help > > > + This option is used to enable ZynqMP QSPI controller driver > which > > > + is used to communicate with qspi flash devices. > > > > I've commented this before, what is the reason for adding spi kconfig > > entry in arch area instead of drivers/spi? > > I might have missed it, Will move to drivers/spi > > > > > + > > > config ZYNQMP_USB > > > bool "Configure ZynqMP USB" > > > > > > diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > > > b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > > > new file mode 100644 > > > index 000..5e2926e > > > --- /dev/null > > > +++ b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > > > @@ -0,0 +1,154 @@ > > > +/* > > > + * (C) Copyright 2014 - 2015 Xilinx > > > + * > > > + * Xilinx ZynqMP Quad-SPI(QSPI) controller driver (master mode > > > +only) > > > + * > > > + * SPDX-License-Identifier:GPL-2.0+ > > > + */ > > > + > > > +#ifndef _ASM_ARCH_ZYNQMP_QSPI_H_ > > > +#define _ASM_ARCH_ZYNQMP_QSPI_H_ > > > + > > > +#define ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK BIT(29) > > > +#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASK(3 << 30) > > > +#define ZYNQMP_QSPI_CONFIG_DMA_MODE(2 << 30) > > > +#define ZYNQMP_QSPI_CONFIG_CPHA_MASK BIT(2) > > > +#define ZYNQMP_QSPI_CONFIG_CPOL_MASK BIT(1) > > > + > > > +/* QSPI MIO's count for different connection topologies */ > > > +#define ZYNQMP_QSPI_MIO_NUM_QSPI0 6 > > > +#define ZYNQMP_QSPI_MIO_NUM_QSPI1 5 > > > +#define ZYNQMP_QSPI_MIO_NUM_QSPI1_CS 1 > > > + > > > +/* > > > + * QSPI Interrupt Registers bit Masks > > > + * > > > + * All the four interrupt registers (Status/Mask/Enable/Disable) >
Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver
Hi Jagan, > -Original Message- > From: Jagan Teki [mailto:ja...@amarulasolutions.com] > Sent: Tuesday, January 23, 2018 10:41 PM > To: Siva Durga Prasad Paladugu > Cc: U-Boot-Denx ; Siva Durga Prasad Paladugu > > Subject: Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for > ZynqMP qspi driver > > On Thu, Jan 4, 2018 at 1:07 PM, Siva Durga Prasad Paladugu > wrote: > > This patch adds qspi driver support for ZynqMP SoC. This driver is > > responsible for communicating with qspi flash devices. > > > > Signed-off-by: Siva Durga Prasad Paladugu > > --- > > Changes from v1: > > - Rebased on top of latest master > > - Moved macro definitions to .h file as per comment > > - Fixed magic values with macros as per comment > > --- > > arch/arm/cpu/armv8/zynqmp/Kconfig | 7 + > > arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h | 154 ++ > > drivers/spi/Makefile | 1 + > > drivers/spi/zynqmp_qspi.c | 678 > + > > Was this gqspi like linux spi-zynqmp-gqspi.c or different? Yes. > > > 4 files changed, 840 insertions(+) > > create mode 100644 arch/arm/include/asm/arch- > zynqmp/zynqmp_qspi.h > > create mode 100644 drivers/spi/zynqmp_qspi.c > > > > diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig > > b/arch/arm/cpu/armv8/zynqmp/Kconfig > > index 3f922b4..2fe4f71 100644 > > --- a/arch/arm/cpu/armv8/zynqmp/Kconfig > > +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig > > @@ -65,6 +65,13 @@ config PMUFW_INIT_FILE > > Include external PMUFW (Platform Management Unit FirmWare) to > > a Xilinx bootable image (boot.bin). > > > > +config ZYNQMP_QSPI > > + bool "Configure ZynqMP QSPI" > > + select DM_SPI > > + help > > + This option is used to enable ZynqMP QSPI controller driver which > > + is used to communicate with qspi flash devices. > > I've commented this before, what is the reason for adding spi kconfig entry > in arch area instead of drivers/spi? I might have missed it, Will move to drivers/spi > > > + > > config ZYNQMP_USB > > bool "Configure ZynqMP USB" > > > > diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > > b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > > new file mode 100644 > > index 000..5e2926e > > --- /dev/null > > +++ b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > > @@ -0,0 +1,154 @@ > > +/* > > + * (C) Copyright 2014 - 2015 Xilinx > > + * > > + * Xilinx ZynqMP Quad-SPI(QSPI) controller driver (master mode only) > > + * > > + * SPDX-License-Identifier:GPL-2.0+ > > + */ > > + > > +#ifndef _ASM_ARCH_ZYNQMP_QSPI_H_ > > +#define _ASM_ARCH_ZYNQMP_QSPI_H_ > > + > > +#define ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK BIT(29) > > +#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASK(3 << 30) > > +#define ZYNQMP_QSPI_CONFIG_DMA_MODE(2 << 30) > > +#define ZYNQMP_QSPI_CONFIG_CPHA_MASK BIT(2) > > +#define ZYNQMP_QSPI_CONFIG_CPOL_MASK BIT(1) > > + > > +/* QSPI MIO's count for different connection topologies */ > > +#define ZYNQMP_QSPI_MIO_NUM_QSPI0 6 > > +#define ZYNQMP_QSPI_MIO_NUM_QSPI1 5 > > +#define ZYNQMP_QSPI_MIO_NUM_QSPI1_CS 1 > > + > > +/* > > + * QSPI Interrupt Registers bit Masks > > + * > > + * All the four interrupt registers (Status/Mask/Enable/Disable) have > > +the same > > + * bit definitions. > > + */ > > +#define ZYNQMP_QSPI_IXR_TXNFULL_MASK 0x0004 /* QSPI TX > FIFO Overflow */ > > +#define ZYNQMP_QSPI_IXR_TXFULL_MASK0x0008 /* QSPI TX > FIFO is full */ > > +#define ZYNQMP_QSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX > FIFO Not Empty */ > > +#define ZYNQMP_QSPI_IXR_GFEMTY_MASK0x0080 /* QSPI > Generic FIFO Empty */ > > +#define ZYNQMP_QSPI_IXR_ALL_MASK > (ZYNQMP_QSPI_IXR_TXNFULL_MASK | \ > > + ZYNQMP_QSPI_IXR_RXNEMTY_MASK) > > + > > +/* > > + * QSPI Enable Register bit Masks > > + * > > + * This register is used to enable or disable the QSPI controller */ > > +#define ZYNQMP_QSPI_ENABLE_ENABLE_MASK 0x0001 /* QSPI > Enable Bit > > +Mask */ > > + > > +#define ZYNQMP_QSPI_GFIFO_LOW_BUS BIT(14) > > +#define ZYNQMP_QSPI_GFIFO_CS_LOWER BIT(12) > > +#define ZYNQMP_QSPI_GFIFO_UP_BUS BIT(15) > > +#define ZYNQMP_QSPI_GFIFO_CS_UPPER
Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver
On Thu, Jan 4, 2018 at 1:07 PM, Siva Durga Prasad Paladugu wrote: > This patch adds qspi driver support for ZynqMP SoC. This > driver is responsible for communicating with qspi flash > devices. > > Signed-off-by: Siva Durga Prasad Paladugu > --- > Changes from v1: > - Rebased on top of latest master > - Moved macro definitions to .h file as per comment > - Fixed magic values with macros as per comment > --- > arch/arm/cpu/armv8/zynqmp/Kconfig | 7 + > arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h | 154 ++ > drivers/spi/Makefile | 1 + > drivers/spi/zynqmp_qspi.c | 678 > + Was this gqspi like linux spi-zynqmp-gqspi.c or different? > 4 files changed, 840 insertions(+) > create mode 100644 arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > create mode 100644 drivers/spi/zynqmp_qspi.c > > diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig > b/arch/arm/cpu/armv8/zynqmp/Kconfig > index 3f922b4..2fe4f71 100644 > --- a/arch/arm/cpu/armv8/zynqmp/Kconfig > +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig > @@ -65,6 +65,13 @@ config PMUFW_INIT_FILE > Include external PMUFW (Platform Management Unit FirmWare) to > a Xilinx bootable image (boot.bin). > > +config ZYNQMP_QSPI > + bool "Configure ZynqMP QSPI" > + select DM_SPI > + help > + This option is used to enable ZynqMP QSPI controller driver which > + is used to communicate with qspi flash devices. I've commented this before, what is the reason for adding spi kconfig entry in arch area instead of drivers/spi? > + > config ZYNQMP_USB > bool "Configure ZynqMP USB" > > diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > new file mode 100644 > index 000..5e2926e > --- /dev/null > +++ b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > @@ -0,0 +1,154 @@ > +/* > + * (C) Copyright 2014 - 2015 Xilinx > + * > + * Xilinx ZynqMP Quad-SPI(QSPI) controller driver (master mode only) > + * > + * SPDX-License-Identifier:GPL-2.0+ > + */ > + > +#ifndef _ASM_ARCH_ZYNQMP_QSPI_H_ > +#define _ASM_ARCH_ZYNQMP_QSPI_H_ > + > +#define ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK BIT(29) > +#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASK(3 << 30) > +#define ZYNQMP_QSPI_CONFIG_DMA_MODE(2 << 30) > +#define ZYNQMP_QSPI_CONFIG_CPHA_MASK BIT(2) > +#define ZYNQMP_QSPI_CONFIG_CPOL_MASK BIT(1) > + > +/* QSPI MIO's count for different connection topologies */ > +#define ZYNQMP_QSPI_MIO_NUM_QSPI0 6 > +#define ZYNQMP_QSPI_MIO_NUM_QSPI1 5 > +#define ZYNQMP_QSPI_MIO_NUM_QSPI1_CS 1 > + > +/* > + * QSPI Interrupt Registers bit Masks > + * > + * All the four interrupt registers (Status/Mask/Enable/Disable) have the > same > + * bit definitions. > + */ > +#define ZYNQMP_QSPI_IXR_TXNFULL_MASK 0x0004 /* QSPI TX FIFO Overflow */ > +#define ZYNQMP_QSPI_IXR_TXFULL_MASK0x0008 /* QSPI TX FIFO is full */ > +#define ZYNQMP_QSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX FIFO Not Empty > */ > +#define ZYNQMP_QSPI_IXR_GFEMTY_MASK0x0080 /* QSPI Generic FIFO Empty > */ > +#define ZYNQMP_QSPI_IXR_ALL_MASK (ZYNQMP_QSPI_IXR_TXNFULL_MASK | \ > + ZYNQMP_QSPI_IXR_RXNEMTY_MASK) > + > +/* > + * QSPI Enable Register bit Masks > + * > + * This register is used to enable or disable the QSPI controller > + */ > +#define ZYNQMP_QSPI_ENABLE_ENABLE_MASK 0x0001 /* QSPI Enable Bit Mask */ > + > +#define ZYNQMP_QSPI_GFIFO_LOW_BUS BIT(14) > +#define ZYNQMP_QSPI_GFIFO_CS_LOWER BIT(12) > +#define ZYNQMP_QSPI_GFIFO_UP_BUS BIT(15) > +#define ZYNQMP_QSPI_GFIFO_CS_UPPER BIT(13) > +#define ZYNQMP_QSPI_SPI_MODE_QSPI (3 << 10) > +#define ZYNQMP_QSPI_SPI_MODE_SPI BIT(10) > +#define ZYNQMP_QSPI_SPI_MODE_DUAL_SPI (2 << 10) > +#define ZYNQMP_QSPI_IMD_DATA_CS_ASSERT 5 > +#define ZYNQMP_QSPI_IMD_DATA_CS_DEASSERT 5 > +#define ZYNQMP_QSPI_GFIFO_TX BIT(16) > +#define ZYNQMP_QSPI_GFIFO_RX BIT(17) > +#define ZYNQMP_QSPI_GFIFO_STRIPE_MASK BIT(18) > +#define ZYNQMP_QSPI_GFIFO_IMD_MASK 0xFF > +#define ZYNQMP_QSPI_GFIFO_EXP_MASK BIT(9) > +#define ZYNQMP_QSPI_GFIFO_DATA_XFR_MASKBIT(8) > +#define ZYNQMP_QSPI_STRT_GEN_FIFO BIT(28) > +#define ZYNQMP_QSPI_GEN_FIFO_STRT_MOD BIT(29) > +#define ZYNQMP_QSPI_GFIFO_WP_HOLD BIT(19) > +#define ZYNQMP_QSPI_BAUD_DIV_MASK (7 << 3) > +#define ZYNQMP_QSPI_DFLT_BAUD_RATE_DIV BIT(3) > +#define ZYNQMP_QSPI_GFIFO_ALL_INT_MASK 0xFBE > +#define ZYNQMP_QSPI_DMA_DST_I_STS_DONE BIT(1) > +#define ZYNQMP_QSPI_DMA_DST_I_STS_MASK 0xFE > +#define MODEBITS 0x6 > + > +#define QUAD_OUT_READ_CMD 0x6B > +#define QUAD_PAGE_PROGRAM_CMD 0x32 > +#define DUAL_OUTPUT_FASTRD_CMD 0x3B > + > +#define ZYNQMP_QSPI_GFIFO_SELECT BIT(0) > + > +#define Z
Re: [U-Boot] [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi driver
Hi Jagan, Ping! Thanks, Siva > -Original Message- > From: Siva Durga Prasad Paladugu [mailto:siva.durga.palad...@xilinx.com] > Sent: Thursday, January 04, 2018 1:08 PM > To: u-boot@lists.denx.de > Cc: jagannadh.t...@gmail.com; Siva Durga Prasad Paladugu > > Subject: [PATCH v2 1/2] spi: zynqmp_qspi: Add support for ZynqMP qspi > driver > > This patch adds qspi driver support for ZynqMP SoC. This driver is > responsible for communicating with qspi flash devices. > > Signed-off-by: Siva Durga Prasad Paladugu > --- > Changes from v1: > - Rebased on top of latest master > - Moved macro definitions to .h file as per comment > - Fixed magic values with macros as per comment > --- > arch/arm/cpu/armv8/zynqmp/Kconfig | 7 + > arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h | 154 ++ > drivers/spi/Makefile | 1 + > drivers/spi/zynqmp_qspi.c | 678 > + > 4 files changed, 840 insertions(+) > create mode 100644 arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > create mode 100644 drivers/spi/zynqmp_qspi.c > > diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig > b/arch/arm/cpu/armv8/zynqmp/Kconfig > index 3f922b4..2fe4f71 100644 > --- a/arch/arm/cpu/armv8/zynqmp/Kconfig > +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig > @@ -65,6 +65,13 @@ config PMUFW_INIT_FILE > Include external PMUFW (Platform Management Unit FirmWare) > to > a Xilinx bootable image (boot.bin). > > +config ZYNQMP_QSPI > + bool "Configure ZynqMP QSPI" > + select DM_SPI > + help > + This option is used to enable ZynqMP QSPI controller driver which > + is used to communicate with qspi flash devices. > + > config ZYNQMP_USB > bool "Configure ZynqMP USB" > > diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > new file mode 100644 > index 000..5e2926e > --- /dev/null > +++ b/arch/arm/include/asm/arch-zynqmp/zynqmp_qspi.h > @@ -0,0 +1,154 @@ > +/* > + * (C) Copyright 2014 - 2015 Xilinx > + * > + * Xilinx ZynqMP Quad-SPI(QSPI) controller driver (master mode only) > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef _ASM_ARCH_ZYNQMP_QSPI_H_ > +#define _ASM_ARCH_ZYNQMP_QSPI_H_ > + > +#define ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK BIT(29) > +#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASK (3 << 30) > +#define ZYNQMP_QSPI_CONFIG_DMA_MODE (2 << 30) > +#define ZYNQMP_QSPI_CONFIG_CPHA_MASK BIT(2) > +#define ZYNQMP_QSPI_CONFIG_CPOL_MASK BIT(1) > + > +/* QSPI MIO's count for different connection topologies */ > +#define ZYNQMP_QSPI_MIO_NUM_QSPI06 > +#define ZYNQMP_QSPI_MIO_NUM_QSPI15 > +#define ZYNQMP_QSPI_MIO_NUM_QSPI1_CS 1 > + > +/* > + * QSPI Interrupt Registers bit Masks > + * > + * All the four interrupt registers (Status/Mask/Enable/Disable) have > +the same > + * bit definitions. > + */ > +#define ZYNQMP_QSPI_IXR_TXNFULL_MASK 0x0004 /* QSPI TX FIFO > Overflow */ > +#define ZYNQMP_QSPI_IXR_TXFULL_MASK 0x0008 /* QSPI TX FIFO > is full */ > +#define ZYNQMP_QSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI > RX FIFO Not Empty */ > +#define ZYNQMP_QSPI_IXR_GFEMTY_MASK 0x0080 /* QSPI Generic > FIFO Empty */ > +#define ZYNQMP_QSPI_IXR_ALL_MASK > (ZYNQMP_QSPI_IXR_TXNFULL_MASK | \ > + > ZYNQMP_QSPI_IXR_RXNEMTY_MASK) > + > +/* > + * QSPI Enable Register bit Masks > + * > + * This register is used to enable or disable the QSPI controller */ > +#define ZYNQMP_QSPI_ENABLE_ENABLE_MASK 0x0001 /* QSPI > Enable Bit Mask */ > + > +#define ZYNQMP_QSPI_GFIFO_LOW_BUSBIT(14) > +#define ZYNQMP_QSPI_GFIFO_CS_LOWER BIT(12) > +#define ZYNQMP_QSPI_GFIFO_UP_BUS BIT(15) > +#define ZYNQMP_QSPI_GFIFO_CS_UPPER BIT(13) > +#define ZYNQMP_QSPI_SPI_MODE_QSPI(3 << 10) > +#define ZYNQMP_QSPI_SPI_MODE_SPI BIT(10) > +#define ZYNQMP_QSPI_SPI_MODE_DUAL_SPI(2 << 10) > +#define ZYNQMP_QSPI_IMD_DATA_CS_ASSERT 5 > +#define ZYNQMP_QSPI_IMD_DATA_CS_DEASSERT 5 > +#define ZYNQMP_QSPI_GFIFO_TX BIT(16) > +#define ZYNQMP_QSPI_GFIFO_RX BIT(17) > +#define ZYNQMP_QSPI_GFIFO_STRIPE_MASKBIT(18) > +#define ZYNQMP_QSPI_GFIFO_IMD_MASK 0xFF > +#define ZYNQMP_QSPI_GFIFO_EXP_MASK BIT(9) > +#define ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK BIT(8) > +#define ZYNQMP_QSPI_STRT_GEN_FIFOBIT(28) > +#define ZYNQMP_QSPI_GEN_FIFO_STRT_MODBIT(29) > +#define ZYNQMP_QSPI_GFIFO_WP_HOLDBIT(19) > +#define ZYNQMP_QSPI_BAUD_DIV_MASK(7 << 3) > +#define ZYNQMP_QSPI_DFLT_BAUD_RATE_DIV BIT(3) > +#define ZYNQMP_QSPI_GFIFO_ALL_INT_MASK 0xFBE > +#define ZYNQMP_QSPI_DMA_DST_I_STS_DONE BIT(1) > +#define ZYNQMP_QSPI_DMA_DST_I_STS_MASK 0xFE > +#define MODEBITS 0x6 > + > +#define QUAD_OUT_READ_CMD0x6B > +#define QUAD_PAGE_PROGRAM_CMD0x32 > +#define DUAL_OUTPUT_FASTRD_CMD 0x3B > +
