On 08/12/2017 10:05 AM, Chee, Tien Fong wrote:
> On Jum, 2017-08-11 at 17:01 +0200, Marek Vasut wrote:
>> On 08/10/2017 06:51 AM, Chee, Tien Fong wrote:
>>>
>>> On Rab, 2017-08-09 at 10:20 +0200, Marek Vasut wrote:
On 08/09/2017 07:07 AM, Chee, Tien Fong wrote:
>
>
> On Sel,
On Jum, 2017-08-11 at 17:01 +0200, Marek Vasut wrote:
> On 08/10/2017 06:51 AM, Chee, Tien Fong wrote:
> >
> > On Rab, 2017-08-09 at 10:20 +0200, Marek Vasut wrote:
> > >
> > > On 08/09/2017 07:07 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Sel, 2017-08-08 at 11:29 +0200, Marek Vasut
On 08/10/2017 06:51 AM, Chee, Tien Fong wrote:
> On Rab, 2017-08-09 at 10:20 +0200, Marek Vasut wrote:
>> On 08/09/2017 07:07 AM, Chee, Tien Fong wrote:
>>>
>>> On Sel, 2017-08-08 at 11:29 +0200, Marek Vasut wrote:
On 08/08/2017 11:12 AM, tien.fong.c...@intel.com wrote:
>
>
>
On Rab, 2017-08-09 at 10:20 +0200, Marek Vasut wrote:
> On 08/09/2017 07:07 AM, Chee, Tien Fong wrote:
> >
> > On Sel, 2017-08-08 at 11:29 +0200, Marek Vasut wrote:
> > >
> > > On 08/08/2017 11:12 AM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
On 08/09/2017 07:07 AM, Chee, Tien Fong wrote:
> On Sel, 2017-08-08 at 11:29 +0200, Marek Vasut wrote:
>> On 08/08/2017 11:12 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> Function for checking FPGA early release setting which is defined
>>> by
On Sel, 2017-08-08 at 11:29 +0200, Marek Vasut wrote:
> On 08/08/2017 11:12 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Function for checking FPGA early release setting which is defined
> > by user in FDT chosen section. This function would
On 08/08/2017 11:12 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Function for checking FPGA early release setting which is defined
> by user in FDT chosen section. This function would be used by
> later driver in decision applying appropriate FPGA
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