On 02/04/2018 05:40 AM, Simon Glass wrote:
> Hi York,
>
> On 24 January 2018 at 12:04, York Sun wrote:
>> For DDR4, command/address delay in mode registers and parity latency
>> in timing config register are only needed for UDIMMs, but not RDIMMs.
>> Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
>> dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Use
>> hexadecimal format for printing RCW (register control word) registers.
>>
>> Signed-off-by: York Sun
>> ---
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>> drivers/ddr/fsl/ctrl_regs.c| 32 +---
>> drivers/ddr/fsl/ddr4_dimm_params.c | 2 ++
>> drivers/ddr/fsl/interactive.c | 9 +++--
>> include/fsl_ddr_sdram.h| 1 +
>> 4 files changed, 35 insertions(+), 9 deletions(-)
>
> What do you think about moving this into drivers/ram (separate from
> this patch)? Do you think it could use the uclass?
Simon,
Moving to drivers/ram is not a problem. My concern is it is worth the
effort. Legacy PowerPC-based SoCs are still alive but I don't see any
new products coming. ARM-based SoCs will move to ATF (or alike) boots
first model. Once ATF boots first, U-Boot will no longer need this
driver (PowerPC SoCs still use it though). Let's discuss this again a
few months later when I may have a better vision.
York
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