Re: [U-Boot] [PATCH v5 03/10] dm: spi: add BCM63xx SPI driver

[Álvaro Fernández Rojas]

Hello Jagan,


El 10/08/2017 a las 11:25, Jagan Teki escribió:

On Sun, Jul 30, 2017 at 5:43 PM, Álvaro Fernández Rojas
 wrote:

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c

Signed-off-by: Álvaro Fernández Rojas 
Reviewed-by: Simon Glass 
Reviewed-by: Daniel Schwierzeck 
---
  v5: Introduce changes suggested by Jagan Teki:
   - Use long structure instead of a custom bmips_spi_hw structure.
   - Define constants for each SPI core.
  v4: Introduce changes suggested by Jagan Teki:
   - Add data for each HW controller instead of having two separate configs.
   - Also check clock and reset returns as suggested by Simon Glass for HSSPI.
  v3: rename BCM6338 SPI driver to BCM6348
   switch to devfdt_get_addr_size_index()
  v2: no changes

  drivers/spi/Kconfig   |   8 +
  drivers/spi/Makefile  |   1 +
  drivers/spi/bcm63xx_spi.c | 434 ++
  3 files changed, 443 insertions(+)
  create mode 100644 drivers/spi/bcm63xx_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8a8e8e480f..511643607b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -40,6 +40,14 @@ config ATMEL_SPI
   many AT91 (ARM) chips. This driver can be used to access
   the SPI Flash, such as AT25DF321.

+config BCM63XX_SPI
+   bool "BCM6348 SPI driver"
+   depends on ARCH_BMIPS
+   help
+ Enable the BCM6348/BCM6358 SPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding these Broadcom
+ SPI cores.
+
  config CADENCE_QSPI
 bool "Cadence QSPI driver"
 help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 9f8b86de76..d9802dd8c3 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
  obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
  obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
+obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
  obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
  obj-$(CONFIG_CF_SPI) += cf_spi.o
  obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c
new file mode 100644
index 00..904db2b7c7
--- /dev/null
+++ b/drivers/spi/bcm63xx_spi.c
@@ -0,0 +1,434 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas 
+ *
+ * Derived from linux/drivers/spi/spi-bcm63xx.c:
+ * Copyright (C) 2009-2012 Florian Fainelli 
+ * Copyright (C) 2010 Tanguy Bouzeloc 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* BCM6348 SPI core */
+#define SPI_6348_CLK   0x06
+#define SPI_6348_CMD   0x00
+#define SPI_6348_CTL   0x40
+#define SPI_6348_CTL_SHIFT 6
+#define SPI_6348_FILL  0x07
+#define SPI_6348_IR_MASK   0x04
+#define SPI_6348_IR_STAT   0x02
+#define SPI_6348_RX0x80
+#define SPI_6348_RX_SIZE   0x3f
+#define SPI_6348_TX0x41
+#define SPI_6348_TX_SIZE   0x3f
+
+/* BCM6358 SPI core */
+#define SPI_6358_CLK   0x706
+#define SPI_6358_CMD   0x700
+#define SPI_6358_CTL   0x000
+#define SPI_6358_CTL_SHIFT 14
+#define SPI_6358_FILL  0x707
+#define SPI_6358_IR_MASK   0x702
+#define SPI_6358_IR_STAT   0x704
+#define SPI_6358_RX0x400
+#define SPI_6358_RX_SIZE   0x220
+#define SPI_6358_TX0x002
+#define SPI_6358_TX_SIZE   0x21e
+
+/* SPI Clock register */
+#define SPI_CLK_SHIFT  0
+#define SPI_CLK_20MHZ  (0 << SPI_CLK_SHIFT)
+#define SPI_CLK_0_391MHZ   (1 << SPI_CLK_SHIFT)
+#define SPI_CLK_0_781MHZ   (2 << SPI_CLK_SHIFT)
+#define SPI_CLK_1_563MHZ   (3 << SPI_CLK_SHIFT)
+#define SPI_CLK_3_125MHZ   (4 << SPI_CLK_SHIFT)
+#define SPI_CLK_6_250MHZ   (5 << SPI_CLK_SHIFT)
+#define SPI_CLK_12_50MHZ   (6 << SPI_CLK_SHIFT)
+#define SPI_CLK_25MHZ  (7 << SPI_CLK_SHIFT)
+#define SPI_CLK_MASK   (7 << SPI_CLK_SHIFT)
+#define SPI_CLK_SSOFF_SHIFT3
+#define SPI_CLK_SSOFF_2(2 << SPI_CLK_SSOFF_SHIFT)
+#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT)
+#define SPI_CLK_BSWAP_SHIFT7
+#define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)
+
+/* SPI Command register */
+#define SPI_CMD_OP_SHIFT   0
+#define SPI_CMD_OP_START   (0x3 << SPI_CMD_OP_SHIFT)
+#define SPI_CMD_SLAVE_SHIFT4
+#define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT)
+#define SPI_CMD_PREPEND_SHIFT  8
+#define SPI_CMD_PREPEND_BYTES  0xf
+#define 

Re: [U-Boot] [PATCH v5 03/10] dm: spi: add BCM63xx SPI driver

[Jagan Teki]

On Thu, Aug 10, 2017 at 2:55 PM, Jagan Teki  wrote:
> On Sun, Jul 30, 2017 at 5:43 PM, Álvaro Fernández Rojas
>  wrote:
>> This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c
>>
>> Signed-off-by: Álvaro Fernández Rojas 
>> Reviewed-by: Simon Glass 
>> Reviewed-by: Daniel Schwierzeck 
>> ---
>>  v5: Introduce changes suggested by Jagan Teki:
>>   - Use long structure instead of a custom bmips_spi_hw structure.
>>   - Define constants for each SPI core.
>>  v4: Introduce changes suggested by Jagan Teki:
>>   - Add data for each HW controller instead of having two separate configs.
>>   - Also check clock and reset returns as suggested by Simon Glass for HSSPI.
>>  v3: rename BCM6338 SPI driver to BCM6348
>>   switch to devfdt_get_addr_size_index()
>>  v2: no changes
>>
>>  drivers/spi/Kconfig   |   8 +
>>  drivers/spi/Makefile  |   1 +
>>  drivers/spi/bcm63xx_spi.c | 434 
>> ++
>>  3 files changed, 443 insertions(+)
>>  create mode 100644 drivers/spi/bcm63xx_spi.c
>>
>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> index 8a8e8e480f..511643607b 100644
>> --- a/drivers/spi/Kconfig
>> +++ b/drivers/spi/Kconfig
>> @@ -40,6 +40,14 @@ config ATMEL_SPI
>>   many AT91 (ARM) chips. This driver can be used to access
>>   the SPI Flash, such as AT25DF321.
>>
>> +config BCM63XX_SPI
>> +   bool "BCM6348 SPI driver"
>> +   depends on ARCH_BMIPS
>> +   help
>> + Enable the BCM6348/BCM6358 SPI driver. This driver can be used to
>> + access the SPI NOR flash on platforms embedding these Broadcom
>> + SPI cores.
>> +
>>  config CADENCE_QSPI
>> bool "Cadence QSPI driver"
>> help
>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>> index 9f8b86de76..d9802dd8c3 100644
>> --- a/drivers/spi/Makefile
>> +++ b/drivers/spi/Makefile
>> @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
>>  obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
>>  obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
>>  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
>> +obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
>>  obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
>>  obj-$(CONFIG_CF_SPI) += cf_spi.o
>>  obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
>> diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c
>> new file mode 100644
>> index 00..904db2b7c7
>> --- /dev/null
>> +++ b/drivers/spi/bcm63xx_spi.c
>> @@ -0,0 +1,434 @@
>> +/*
>> + * Copyright (C) 2017 Álvaro Fernández Rojas 
>> + *
>> + * Derived from linux/drivers/spi/spi-bcm63xx.c:
>> + * Copyright (C) 2009-2012 Florian Fainelli 
>> + * Copyright (C) 2010 Tanguy Bouzeloc 
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/* BCM6348 SPI core */
>> +#define SPI_6348_CLK   0x06
>> +#define SPI_6348_CMD   0x00
>> +#define SPI_6348_CTL   0x40
>> +#define SPI_6348_CTL_SHIFT 6
>> +#define SPI_6348_FILL  0x07
>> +#define SPI_6348_IR_MASK   0x04
>> +#define SPI_6348_IR_STAT   0x02
>> +#define SPI_6348_RX0x80
>> +#define SPI_6348_RX_SIZE   0x3f
>> +#define SPI_6348_TX0x41
>> +#define SPI_6348_TX_SIZE   0x3f
>> +
>> +/* BCM6358 SPI core */
>> +#define SPI_6358_CLK   0x706
>> +#define SPI_6358_CMD   0x700
>> +#define SPI_6358_CTL   0x000
>> +#define SPI_6358_CTL_SHIFT 14
>> +#define SPI_6358_FILL  0x707
>> +#define SPI_6358_IR_MASK   0x702
>> +#define SPI_6358_IR_STAT   0x704
>> +#define SPI_6358_RX0x400
>> +#define SPI_6358_RX_SIZE   0x220
>> +#define SPI_6358_TX0x002
>> +#define SPI_6358_TX_SIZE   0x21e
>> +
>> +/* SPI Clock register */
>> +#define SPI_CLK_SHIFT  0
>> +#define SPI_CLK_20MHZ  (0 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_0_391MHZ   (1 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_0_781MHZ   (2 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_1_563MHZ   (3 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_3_125MHZ   (4 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_6_250MHZ   (5 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_12_50MHZ   (6 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_25MHZ  (7 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_MASK   (7 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_SSOFF_SHIFT3
>> +#define SPI_CLK_SSOFF_2(2 << SPI_CLK_SSOFF_SHIFT)
>> +#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT)
>> +#define SPI_CLK_BSWAP_SHIFT7
>> +#define 

Re: [U-Boot] [PATCH v5 03/10] dm: spi: add BCM63xx SPI driver

[Jagan Teki]

On Sun, Jul 30, 2017 at 5:43 PM, Álvaro Fernández Rojas
 wrote:
> This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c
>
> Signed-off-by: Álvaro Fernández Rojas 
> Reviewed-by: Simon Glass 
> Reviewed-by: Daniel Schwierzeck 
> ---
>  v5: Introduce changes suggested by Jagan Teki:
>   - Use long structure instead of a custom bmips_spi_hw structure.
>   - Define constants for each SPI core.
>  v4: Introduce changes suggested by Jagan Teki:
>   - Add data for each HW controller instead of having two separate configs.
>   - Also check clock and reset returns as suggested by Simon Glass for HSSPI.
>  v3: rename BCM6338 SPI driver to BCM6348
>   switch to devfdt_get_addr_size_index()
>  v2: no changes
>
>  drivers/spi/Kconfig   |   8 +
>  drivers/spi/Makefile  |   1 +
>  drivers/spi/bcm63xx_spi.c | 434 
> ++
>  3 files changed, 443 insertions(+)
>  create mode 100644 drivers/spi/bcm63xx_spi.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 8a8e8e480f..511643607b 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -40,6 +40,14 @@ config ATMEL_SPI
>   many AT91 (ARM) chips. This driver can be used to access
>   the SPI Flash, such as AT25DF321.
>
> +config BCM63XX_SPI
> +   bool "BCM6348 SPI driver"
> +   depends on ARCH_BMIPS
> +   help
> + Enable the BCM6348/BCM6358 SPI driver. This driver can be used to
> + access the SPI NOR flash on platforms embedding these Broadcom
> + SPI cores.
> +
>  config CADENCE_QSPI
> bool "Cadence QSPI driver"
> help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 9f8b86de76..d9802dd8c3 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
>  obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
>  obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
>  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
> +obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
>  obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
>  obj-$(CONFIG_CF_SPI) += cf_spi.o
>  obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
> diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c
> new file mode 100644
> index 00..904db2b7c7
> --- /dev/null
> +++ b/drivers/spi/bcm63xx_spi.c
> @@ -0,0 +1,434 @@
> +/*
> + * Copyright (C) 2017 Álvaro Fernández Rojas 
> + *
> + * Derived from linux/drivers/spi/spi-bcm63xx.c:
> + * Copyright (C) 2009-2012 Florian Fainelli 
> + * Copyright (C) 2010 Tanguy Bouzeloc 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* BCM6348 SPI core */
> +#define SPI_6348_CLK   0x06
> +#define SPI_6348_CMD   0x00
> +#define SPI_6348_CTL   0x40
> +#define SPI_6348_CTL_SHIFT 6
> +#define SPI_6348_FILL  0x07
> +#define SPI_6348_IR_MASK   0x04
> +#define SPI_6348_IR_STAT   0x02
> +#define SPI_6348_RX0x80
> +#define SPI_6348_RX_SIZE   0x3f
> +#define SPI_6348_TX0x41
> +#define SPI_6348_TX_SIZE   0x3f
> +
> +/* BCM6358 SPI core */
> +#define SPI_6358_CLK   0x706
> +#define SPI_6358_CMD   0x700
> +#define SPI_6358_CTL   0x000
> +#define SPI_6358_CTL_SHIFT 14
> +#define SPI_6358_FILL  0x707
> +#define SPI_6358_IR_MASK   0x702
> +#define SPI_6358_IR_STAT   0x704
> +#define SPI_6358_RX0x400
> +#define SPI_6358_RX_SIZE   0x220
> +#define SPI_6358_TX0x002
> +#define SPI_6358_TX_SIZE   0x21e
> +
> +/* SPI Clock register */
> +#define SPI_CLK_SHIFT  0
> +#define SPI_CLK_20MHZ  (0 << SPI_CLK_SHIFT)
> +#define SPI_CLK_0_391MHZ   (1 << SPI_CLK_SHIFT)
> +#define SPI_CLK_0_781MHZ   (2 << SPI_CLK_SHIFT)
> +#define SPI_CLK_1_563MHZ   (3 << SPI_CLK_SHIFT)
> +#define SPI_CLK_3_125MHZ   (4 << SPI_CLK_SHIFT)
> +#define SPI_CLK_6_250MHZ   (5 << SPI_CLK_SHIFT)
> +#define SPI_CLK_12_50MHZ   (6 << SPI_CLK_SHIFT)
> +#define SPI_CLK_25MHZ  (7 << SPI_CLK_SHIFT)
> +#define SPI_CLK_MASK   (7 << SPI_CLK_SHIFT)
> +#define SPI_CLK_SSOFF_SHIFT3
> +#define SPI_CLK_SSOFF_2(2 << SPI_CLK_SSOFF_SHIFT)
> +#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT)
> +#define SPI_CLK_BSWAP_SHIFT7
> +#define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)
> +
> +/* SPI Command register */
> +#define SPI_CMD_OP_SHIFT   0
> +#define SPI_CMD_OP_START   (0x3 << SPI_CMD_OP_SHIFT)
> +#define