Hi Stephen,
On Thu, Feb 2, 2012 at 2:07 PM, Stephen Warren swar...@nvidia.com wrote:
On 01/24/2012 04:21 PM, Simon Glass wrote:
This adds clock references to the USB part of the device tree for U-Boot.
The USB timing information may vary between boards sometimes, but for
now we hard-code it in C. This is because all current T2x boards use
the same values, we will deal with T3x later and we first need to agree
on the format for this timing information in the fdt and may in fact
decide that it has no place there.
The patch below does more than what's covered by this description...
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v5:
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments
- Change device tree comment style from // to /* */
arch/arm/dts/tegra20.dtsi | 7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index ec75747..b2e3a40 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -176,6 +176,9 @@
reg = 0xc500 0x4000;
interrupts = 52 ;
phy_type = utmi;
+ clocks = periph_clk 22; /* PERIPH_ID_USBD */
+ dr_mode = otg;
The dr_mode value is board-specific, so should be in tegra-seaboard.dts
not tegra20.dtsi.
Done
For example, on true Seaboard, perhaps USB3 could operate in otg mode
since it's an external port, whereas on Springbank, USB3 is hard-wired
to a keyboard controller, so should be marked host mode only.
OK. I was seeing it as an SOC capability rather than a board feature.
Related, I assume that any port marked as otg needs to have a VBUS
GPIO defined so that it can be turned off in device mode, or is VBUS
controlled by some other mechanism in some cases? Given that, I /think/
you can't actually mark USB3 as otg or device on Seaboard since
there's no VBUS GPIO.
Done. In principle VBUS can be controlled by a bit in the peripheral
controller driving out a VBUS enable line, but that's not how it works
in this case.
--
nvpublic
Regards,
Simon
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