> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, September 11, 2018 12:55 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Lukas Auer
> Subject: [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in
> encoding.h
>
> There is no reason to keep two versions of CSR read/write defines
in encoding.h.
> We already have one set of defines in csr.h, which is from Linux
kernel, and let's
> drop the one in encoding.h.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - new patch to remove CSR read/write defines in encoding.h
>
> arch/riscv/include/asm/encoding.h | 50
---
> 1 file changed, 4 insertions(+), 46 deletions(-)
>
> diff --git a/arch/riscv/include/asm/encoding.h
> b/arch/riscv/include/asm/encoding.h
> index f237a72..9ea50ce 100644
> --- a/arch/riscv/include/asm/encoding.h
> +++ b/arch/riscv/include/asm/encoding.h
> @@ -128,6 +128,7 @@
> ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
>
> #ifdef __riscv
> +
> #ifdef CONFIG_64BIT
> # define MSTATUS_SD MSTATUS64_SD
> # define SSTATUS_SD SSTATUS64_SD
> @@ -141,53 +142,10 @@
> # define MCAUSE_INT MCAUSE32_INT
> # define MCAUSE_CAUSE MCAUSE32_CAUSE
> #endif
> +
> #define RISCV_PGSHIFT 12
> #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
>
> -#ifndef __ASSEMBLER__
> -
> -#ifdef __GNUC__
> -
> -#define read_csr(reg) ({ unsigned long __tmp; \
> - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
> - __tmp; })
> -
> -#define write_csr(reg, _val) ({ \
> -typeof(_val) (val) = (_val); \
> -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
> - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
> -else \
> - asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
> -
> -#define swap_csr(reg, _val) ({ unsigned long __tmp; \
> -typeof(_val) (val) = (_val); \
> -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
> - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
> -else \
> - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
> - __tmp; })
> -
> -#define set_csr(reg, _bit) ({ unsigned long __tmp; \
> -typeof(_bit) (bit) = (_bit); \
> -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
> - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
> -else \
> - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
> - __tmp; })
> -
> -#define clear_csr(reg, _bit) ({ unsigned long __tmp; \
> -typeof(_bit) (bit) = (_bit); \
> -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
> - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
> -else \
> - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
> - __tmp; })
> -
> -#define rdtime() read_csr(time)
> -#define rdcycle() read_csr(cycle)
> -#define rdinstret() read_csr(instret)
> +#endif /* __riscv */
>
> -#endif
> -#endif
> -#endif
> -#endif
> +#endif /* RISCV_CSR_ENCODING_H */
Reviewed-by: Rick Chen
> --
> 2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
