Re: [U-Boot] [linux-sunxi] [PATCH 5/9] sun4i: Rename dram files to dram_sun4i.x
Hi,
On 11/04/2014 05:23 AM, Julian Calaby wrote:
Hi Hans,
On Tue, Nov 4, 2014 at 2:34 AM, Hans de Goede hdego...@redhat.com wrote:
In preparation for adding sun6i dram support.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile| 6 +-
arch/arm/cpu/armv7/sunxi/dram.c | 750
---
arch/arm/cpu/armv7/sunxi/dram_sun4i.c| 750
+++
arch/arm/include/asm/arch-sunxi/dram.h | 171 +-
arch/arm/include/asm/arch-sunxi/dram_sun4i.h | 182 +++
5 files changed, 941 insertions(+), 918 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/sunxi/dram.c
create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun4i.c
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun4i.h
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
b/arch/arm/include/asm/arch-sunxi/dram.h
index 1945f75..9072e68 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -14,172 +14,13 @@
#include linux/types.h
-struct sunxi_dram_reg {
- u32 ccr;/* 0x00 controller configuration register */
- u32 dcr;/* 0x04 dram configuration register */
- u32 iocr; /* 0x08 i/o configuration register */
- u32 csr;/* 0x0c controller status register */
- u32 drr;/* 0x10 dram refresh register */
- u32 tpr0; /* 0x14 dram timing parameters register 0 */
- u32 tpr1; /* 0x18 dram timing parameters register 1 */
- u32 tpr2; /* 0x1c dram timing parameters register 2 */
- u32 gdllcr; /* 0x20 global dll control register */
- u8 res0[0x28];
- u32 rslr0; /* 0x4c rank system latency register */
- u32 rslr1; /* 0x50 rank system latency register */
- u8 res1[0x8];
- u32 rdgr0; /* 0x5c rank dqs gating register */
- u32 rdgr1; /* 0x60 rank dqs gating register */
- u8 res2[0x34];
- u32 odtcr; /* 0x98 odt configuration register */
- u32 dtr0; /* 0x9c data training register 0 */
- u32 dtr1; /* 0xa0 data training register 1 */
- u32 dtar; /* 0xa4 data training address register */
- u32 zqcr0; /* 0xa8 zq control register 0 */
- u32 zqcr1; /* 0xac zq control register 1 */
- u32 zqsr; /* 0xb0 zq status register */
- u32 idcr; /* 0xb4 initializaton delay configure reg */
- u8 res3[0x138];
- u32 mr; /* 0x1f0 mode register */
- u32 emr;/* 0x1f4 extended mode register */
- u32 emr2; /* 0x1f8 extended mode register */
- u32 emr3; /* 0x1fc extended mode register */
- u32 dllctr; /* 0x200 dll control register */
- u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */
- /* 0x208 dll control register 1(byte 1) */
- /* 0x20c dll control register 2(byte 2) */
- /* 0x210 dll control register 3(byte 3) */
- /* 0x214 dll control register 4(byte 4) */
- u32 dqtr0; /* 0x218 dq timing register */
- u32 dqtr1; /* 0x21c dq timing register */
- u32 dqtr2; /* 0x220 dq timing register */
- u32 dqtr3; /* 0x224 dq timing register */
- u32 dqstr; /* 0x228 dqs timing register */
- u32 dqsbtr; /* 0x22c dqsb timing register */
- u32 mcr;/* 0x230 mode configure register */
- u8 res[0x8];
- u32 ppwrsctl; /* 0x23c pad power save control */
- u32 apr;/* 0x240 arbiter period register */
- u32 pldtr; /* 0x244 priority level data threshold reg */
- u8 res5[0x8];
- u32 hpcr[32]; /* 0x250 host port configure register */
- u8 res6[0x10];
- u32 csel; /* 0x2e0 controller select register */
-};
-
-struct dram_para {
- u32 clock;
- u32 mbus_clock;
- u32 type;
- u32 rank_num;
- u32 density;
- u32 io_width;
- u32 bus_width;
- u32 cas;
- u32 zq;
- u32 odt_en;
- u32 size;
- u32 tpr0;
- u32 tpr1;
- u32 tpr2;
- u32 tpr3;
- u32 tpr4;
- u32 tpr5;
- u32 emr1;
- u32 emr2;
- u32 emr3;
- u32 dqs_gating_delay;
- u32 active_windowing;
-};
-
-#define DRAM_CCR_COMMAND_RATE_1T (0x1 5)
-#define DRAM_CCR_DQS_GATE (0x1 14)
-#define DRAM_CCR_DQS_DRIFT_COMP (0x1 17)
-#define DRAM_CCR_ITM_OFF (0x1 28)
-#define DRAM_CCR_DATA_TRAINING (0x1 30)
-#define DRAM_CCR_INIT (0x1 31)
-
-#define DRAM_MEMORY_TYPE_DDR1 1
-#define
Re: [U-Boot] [linux-sunxi] [PATCH 5/9] sun4i: Rename dram files to dram_sun4i.x
Hi Hans,
On Tue, Nov 4, 2014 at 2:34 AM, Hans de Goede hdego...@redhat.com wrote:
In preparation for adding sun6i dram support.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile| 6 +-
arch/arm/cpu/armv7/sunxi/dram.c | 750
---
arch/arm/cpu/armv7/sunxi/dram_sun4i.c| 750
+++
arch/arm/include/asm/arch-sunxi/dram.h | 171 +-
arch/arm/include/asm/arch-sunxi/dram_sun4i.h | 182 +++
5 files changed, 941 insertions(+), 918 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/sunxi/dram.c
create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun4i.c
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun4i.h
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
b/arch/arm/include/asm/arch-sunxi/dram.h
index 1945f75..9072e68 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -14,172 +14,13 @@
#include linux/types.h
-struct sunxi_dram_reg {
- u32 ccr;/* 0x00 controller configuration register */
- u32 dcr;/* 0x04 dram configuration register */
- u32 iocr; /* 0x08 i/o configuration register */
- u32 csr;/* 0x0c controller status register */
- u32 drr;/* 0x10 dram refresh register */
- u32 tpr0; /* 0x14 dram timing parameters register 0 */
- u32 tpr1; /* 0x18 dram timing parameters register 1 */
- u32 tpr2; /* 0x1c dram timing parameters register 2 */
- u32 gdllcr; /* 0x20 global dll control register */
- u8 res0[0x28];
- u32 rslr0; /* 0x4c rank system latency register */
- u32 rslr1; /* 0x50 rank system latency register */
- u8 res1[0x8];
- u32 rdgr0; /* 0x5c rank dqs gating register */
- u32 rdgr1; /* 0x60 rank dqs gating register */
- u8 res2[0x34];
- u32 odtcr; /* 0x98 odt configuration register */
- u32 dtr0; /* 0x9c data training register 0 */
- u32 dtr1; /* 0xa0 data training register 1 */
- u32 dtar; /* 0xa4 data training address register */
- u32 zqcr0; /* 0xa8 zq control register 0 */
- u32 zqcr1; /* 0xac zq control register 1 */
- u32 zqsr; /* 0xb0 zq status register */
- u32 idcr; /* 0xb4 initializaton delay configure reg */
- u8 res3[0x138];
- u32 mr; /* 0x1f0 mode register */
- u32 emr;/* 0x1f4 extended mode register */
- u32 emr2; /* 0x1f8 extended mode register */
- u32 emr3; /* 0x1fc extended mode register */
- u32 dllctr; /* 0x200 dll control register */
- u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */
- /* 0x208 dll control register 1(byte 1) */
- /* 0x20c dll control register 2(byte 2) */
- /* 0x210 dll control register 3(byte 3) */
- /* 0x214 dll control register 4(byte 4) */
- u32 dqtr0; /* 0x218 dq timing register */
- u32 dqtr1; /* 0x21c dq timing register */
- u32 dqtr2; /* 0x220 dq timing register */
- u32 dqtr3; /* 0x224 dq timing register */
- u32 dqstr; /* 0x228 dqs timing register */
- u32 dqsbtr; /* 0x22c dqsb timing register */
- u32 mcr;/* 0x230 mode configure register */
- u8 res[0x8];
- u32 ppwrsctl; /* 0x23c pad power save control */
- u32 apr;/* 0x240 arbiter period register */
- u32 pldtr; /* 0x244 priority level data threshold reg */
- u8 res5[0x8];
- u32 hpcr[32]; /* 0x250 host port configure register */
- u8 res6[0x10];
- u32 csel; /* 0x2e0 controller select register */
-};
-
-struct dram_para {
- u32 clock;
- u32 mbus_clock;
- u32 type;
- u32 rank_num;
- u32 density;
- u32 io_width;
- u32 bus_width;
- u32 cas;
- u32 zq;
- u32 odt_en;
- u32 size;
- u32 tpr0;
- u32 tpr1;
- u32 tpr2;
- u32 tpr3;
- u32 tpr4;
- u32 tpr5;
- u32 emr1;
- u32 emr2;
- u32 emr3;
- u32 dqs_gating_delay;
- u32 active_windowing;
-};
-
-#define DRAM_CCR_COMMAND_RATE_1T (0x1 5)
-#define DRAM_CCR_DQS_GATE (0x1 14)
-#define DRAM_CCR_DQS_DRIFT_COMP (0x1 17)
-#define DRAM_CCR_ITM_OFF (0x1 28)
-#define DRAM_CCR_DATA_TRAINING (0x1 30)
-#define DRAM_CCR_INIT (0x1 31)
-
-#define DRAM_MEMORY_TYPE_DDR1 1
-#define DRAM_MEMORY_TYPE_DDR2 2
-#define
Re: [U-Boot] [linux-sunxi] [PATCH 5/9] sun4i: Rename dram files to dram_sun4i.x
On Mon, Nov 3, 2014 at 11:34 PM, Hans de Goede hdego...@redhat.com wrote:
In preparation for adding sun6i dram support.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile| 6 +-
arch/arm/cpu/armv7/sunxi/dram.c | 750
---
arch/arm/cpu/armv7/sunxi/dram_sun4i.c| 750
+++
arch/arm/include/asm/arch-sunxi/dram.h | 171 +-
arch/arm/include/asm/arch-sunxi/dram_sun4i.h | 182 +++
5 files changed, 941 insertions(+), 918 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/sunxi/dram.c
create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun4i.c
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun4i.h
Probably be better to run git format-patch with -M so it doesn't
generate a whole diff. Though it doesn't make much of a difference
since you'll be the one committing and pushing, it does make the
mail shorter and easier to read. :)
ChenYu
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index b3a3601..48cca0b 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -28,9 +28,9 @@ endif
endif
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_MACH_SUN4I) += dram.o
-obj-$(CONFIG_MACH_SUN5I) += dram.o
-obj-$(CONFIG_MACH_SUN7I) += dram.o
+obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
deleted file mode 100644
index dc9fdb9..000
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ /dev/null
@@ -1,750 +0,0 @@
-/*
- * sunxi DRAM controller initialization
- * (C) Copyright 2012 Henrik Nordstrom hen...@henriknordstrom.net
- * (C) Copyright 2013 Luke Kenneth Casson Leighton l...@lkcl.net
- *
- * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
- * and earlier U-Boot Allwiner A10 SPL work
- *
- * (C) Copyright 2007-2012
- * Allwinner Technology Co., Ltd. www.allwinnertech.com
- * Berg Xing bergx...@allwinnertech.com
- * Tom Cubie tangli...@allwinnertech.com
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-/*
- * Unfortunately the only documentation we have on the sun7i DRAM
- * controller is Allwinner boot0 + boot1 code, and that code uses
- * magic numbers shifts with no explanations. Hence this code is
- * rather undocumented and full of magic.
- */
-
-#include common.h
-#include asm/io.h
-#include asm/arch/clock.h
-#include asm/arch/dram.h
-#include asm/arch/timer.h
-#include asm/arch/sys_proto.h
-
-#define CPU_CFG_CHIP_VER(n) ((n) 6)
-#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
-#define CPU_CFG_CHIP_REV_A 0x0
-#define CPU_CFG_CHIP_REV_C1 0x1
-#define CPU_CFG_CHIP_REV_C2 0x2
-#define CPU_CFG_CHIP_REV_B 0x3
-
-/*
- * Wait up to 1s for value to be set in given part of reg.
- */
-static void await_completion(u32 *reg, u32 mask, u32 val)
-{
- unsigned long tmo = timer_get_us() + 100;
-
- while ((readl(reg) mask) != val) {
- if (timer_get_us() tmo)
- panic(Timeout initialising DRAM\n);
- }
-}
-
-/*
- * Wait up to 1s for mask to be clear in given reg.
- */
-static inline void await_bits_clear(u32 *reg, u32 mask)
-{
- await_completion(reg, mask, 0);
-}
-
-/*
- * Wait up to 1s for mask to be set in given reg.
- */
-static inline void await_bits_set(u32 *reg, u32 mask)
-{
- await_completion(reg, mask, mask);
-}
-
-/*
- * This performs the external DRAM reset by driving the RESET pin low and
- * then high again. According to the DDR3 spec, the RESET pin needs to be
- * kept low for at least 200 us.
- */
-static void mctl_ddr3_reset(void)
-{
- struct sunxi_dram_reg *dram =
- (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
-#ifdef CONFIG_MACH_SUN4I
- struct sunxi_timer_reg *timer =
- (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
- u32 reg_val;
-
- writel(0, timer-cpu_cfg);
- reg_val = readl(timer-cpu_cfg);
-
- if ((reg_val CPU_CFG_CHIP_VER_MASK) !=
- CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
- setbits_le32(dram-mcr, DRAM_MCR_RESET);
- udelay(200);
- clrbits_le32(dram-mcr, DRAM_MCR_RESET);
- } else
-#endif
- {
- clrbits_le32(dram-mcr, DRAM_MCR_RESET);
- udelay(200);
- setbits_le32(dram-mcr, DRAM_MCR_RESET);
- }
- /* After the RESET pin is de-asserted, the DDR3 spec requires to wait
-* for additional 500 us before driving the CKE pin (Clock Enable)
-* high. The duration of this delay can be configured in the SDR_IDCR
-* (Initialization Delay Configuration Register)
