@ethan.hsieh @ivan.hu,
Response from our BIOS/TPM Engineers:
"Hash Algorithm Bitmap is set in BIOS and it’s based on build
configuration PCD and active PCR’s supported."
This BIOS is also distributed as reference BIOS for IBVs and hence
disabling SM3 would break functionality on other
Hi @ethan.hsieh,
As mentioned in comment #5 above, there is an option to disable SM3 256
algorithm. Please check #5 for a screenshot of the BIOS option
Please give a try and uncheck SM3_256 using below BIOS settings:
Go to Advanced menu> TPM configuration > TCG2 Configuration > enable PCR
Bank
+ Adding Intel TPM Expert
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https://bugs.launchpad.net/bugs/1938678
Title:
[intel] [tgl-h][iotg] [hwe-tpm] Ubuntu Core hangs during bootup on
TGL-H
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Please revert the patch "pinctrl: intel: Add Intel Elkhart Lake pin
controller support" and continue testing
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https://bugs.launchpad.net/bugs/1938413
Title:
Shutdown hangs on EHL board
This is a known issue on EHL, please track the solution here:
https://github.com/thesofproject/linux/issues/2828
As mentioned in the link, Please disable CONFIG_PINCTRL_ELKHARTLAKE=y
for EHL until MR2 BIOS is released.
No need to revert the patch in this case
** Bug watch added:
This is a known issue on EHL, please track the solution here:
https://github.com/thesofproject/linux/issues/2828
As mentioned in the link, Please disable CONFIG_PINCTRL_ELKHARTLAKE=y
for EHL until MR2 BIOS is released.
** Bug watch added: github.com/thesofproject/linux/issues #2828
Please proceed with testing of 1 ethernet port for now. When Canonical
backports the TSN related patches from upstream, can test the
functionality of other port
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@Chris, Response from Intel TPM folks for #44 -
"
I presume by firmware they mean BIOS.
There is no debugger mode left enabled in normal production flows or SKUs for
CSME.
To enable CSME debug mode you'd first unlock the part with an IDLM. I seriously
doubt that the part they have is unlocked.
Can you please also check the BIOS settings -
In EHL CRB, PCH and PSE0 already enabled by default . In order to enable
PSE1, need to change from ‘None’ to ‘Host owned with pin muxed’ in BIOS
BIOS configuration for setting both PSE GBE0 and PSE GBE1 to host owned:
• IntelAdvanced
@Dimitri
Intel has done a few experiments to enable CET on Ubuntu 20.04. Here are
some details:
As my experiment in ubuntu 20.04, the glibc should be update into 2.34.
And busybox should be build on glibc 2.34 (to create initramfs during install
kernel).
Then ubuntu 20.04 can start, and cet
@Canonical,
After speaking to CET experts at Intel, these CET kernel patches are not
needed anymore since the feature is still in development and future
directions might change. Hence closing this LP as Invalid
** Changed in: linux-intel (Ubuntu Focal)
Status: New => Invalid
** Changed
** Changed in: intel
Status: New => Invalid
** Information type changed from Public to Private
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https://bugs.launchpad.net/bugs/1929889
Title:
[TGL][ADL] Enable
** Tags removed: iotg
** Tags added: iotg-adl iotg-ehl iotg-tgl
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https://bugs.launchpad.net/bugs/1943587
Title:
[Ethtool][TSN] Support frame preemption
To manage notifications about
** Tags added: iotg-tgl
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https://bugs.launchpad.net/bugs/1842227
Title:
[TGL] EDAC support for TGL(IoTG)
To manage notifications about this bug go to:
@Kent,
The ECLite driver communication over ISHTP can be tested as follows:
a) "cat /sys/class/thermal/thermal_zone0/temp" - for reading temperature
from EC-Lite.
Note 1: "cat /sys/class/thermal/thermal_zone0/type" should read "acpitz"
- This is EC-Lite's thermal zone
Note 2: You can stress
@Phil,
We need the CONFIG_INTEL_MEI_DAL=m to be enabled as requested in #11,
But both CONFIG_INTEL_MEI_DAL=m and CONFIG_INTEL_MEI_VIRTIO=m are seen
to be disabled.
Can you please check
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