Public bug reported:
An upstream commit added Intel cpu model/microcode checks to disable
TSC_DEADLINE due to cpu errata:
commit bd9240a18edfbfa72e957fc2ba831cf1f13ea073
Author: Peter Zijlstra <pet...@infradead.org>
Date: Wed May 31 17:52:03 2017 +0200
x86/apic: Add TSC_DEADLINE quirk due to errata
That commit is included in the Ubuntu kernels starting at artful v4.13.
However, the commit includes a check for Skylake Xeons, but the microcode
update version number differs based on Skylake Xeon stepping, so an additional
commit is required to correctly check the microcode level of both stepping 3
and stepping 4 Skylake Xeons, and disable/enable TSC_DEADLINE appropriately.
Upstream commit that corrects the check is:
commit 616dd5872e52493863b0202632703eebd51243dc
Author: Len Brown <len.br...@intel.com>
Date: Wed Oct 11 17:16:04 2017 -0400
x86/apic: Update TSC_DEADLINE quirk with additional SKX stepping
Without the additional commit, Skylake Xeon stepping-3 cpus with the fixed
microcode version will incorrectly have their TSC_DEADLINE disabled.
** Affects: linux (Ubuntu)
Importance: Medium
Assignee: Dan Streetman (ddstreet)
Status: In Progress
** Changed in: linux (Ubuntu)
Assignee: (unassigned) => Dan Streetman (ddstreet)
** Changed in: linux (Ubuntu)
Importance: Undecided => Medium
** Changed in: linux (Ubuntu)
Status: New => In Progress
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https://bugs.launchpad.net/bugs/1724612
Title:
x86/apic: Update TSC_DEADLINE quirk with additional SKX stepping
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