Re: Acessing PL devices of Xilinx Zedboard
On 23/11/2020 20:42, jan.som...@dlr.de wrote:
BSP_START_TEXT_SECTION static inline void
arm_cp15_start_set_translation_table_entries(
uint32_t *ttb,
const arm_cp15_start_section_config *config
)
{
if (config->begin != config->end) {
uint32_t i;
uint32_t iend;
uint32_t index_mask;
uint32_t flags;
#ifdef ARM_MMU_USE_SMALL_PAGES
uint32_t *pt;
pt = [ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT];
i = ARM_MMU_SMALL_PAGE_GET_INDEX(config->begin);
iend =
ARM_MMU_SMALL_PAGE_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end));
ARM_MMU_SECT_MVA_ALIGN_UP seems to round the end address up to the next MiB (e.g.
0x40001000 -> 0x4010).
Doesn't that mean that now all 4kiB pages until the next 1MiB will be setup according to
"config->flags" in the loop below, i.e. the same as using 1MiB sections?
This looks like a bug. It should only round up to the next small page.
I would have expected that the address in config->end is rounded up only to the
next 4kiB boundary, but I am not sure if I missed something.
I didn't need the 4KiB MMU for the static sections, so I didn't pay much
attention to this area. I used the small pages for a specialized heap
protection.
--
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Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
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Fax: +49-89-18 94 741 - 08
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RE: Acessing PL devices of Xilinx Zedboard
Hi Sebastian,
I tried to follow the implementation of the small tables, but had some troubles
understanding how it works.
> BSP_START_TEXT_SECTION static inline void
> arm_cp15_start_set_translation_table_entries(
> uint32_t *ttb,
> const arm_cp15_start_section_config *config
> )
> {
> if (config->begin != config->end) {
> uint32_t i;
> uint32_t iend;
> uint32_t index_mask;
> uint32_t flags;
> #ifdef ARM_MMU_USE_SMALL_PAGES
> uint32_t *pt;
>
> pt = [ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT];
> i = ARM_MMU_SMALL_PAGE_GET_INDEX(config->begin);
> iend =
> ARM_MMU_SMALL_PAGE_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end));
ARM_MMU_SECT_MVA_ALIGN_UP seems to round the end address up to the next MiB
(e.g. 0x40001000 -> 0x4010).
Doesn't that mean that now all 4kiB pages until the next 1MiB will be setup
according to "config->flags" in the loop below, i.e. the same as using 1MiB
sections?
I would have expected that the address in config->end is rounded up only to the
next 4kiB boundary, but I am not sure if I missed something.
> index_mask = (1U << (32 - ARM_MMU_SMALL_PAGE_BASE_SHIFT)) - 1U;
> flags = ARM_MMU_SECT_FLAGS_TO_SMALL_PAGE(config->flags);
>
> while (i != iend) {
> pt[i] = (i << ARM_MMU_SMALL_PAGE_BASE_SHIFT) | flags;
> i = (i + 1U) & index_mask;
> }
Cheers,
Jan
> -Original Message-----
> From: users On Behalf Of Sebastian Huber
> Sent: Thursday, November 19, 2020 7:38 AM
> To: users@rtems.org
> Subject: Re: Acessing PL devices of Xilinx Zedboard
>
> Hello Jonathan,
>
> On 18/11/2020 17:00, Jonathan Brandmeyer wrote:
> >
> > Caveat: My information could be a little out of date. We're still
> > running on a pre-release version of RTEMS 5.0. But hopefully this
> > points you in the right direction. In particular, I know that some
> > work has been done to support 4kB pages, but I don't know if the entry
> > point
> arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache
> > currently uses that support or not.
>
> the 4KiB pages MMU configuration was added with this commit:
>
> commit f9648baf65ecec2cd01c96557a677ad6ecc06b11
> Author: Sebastian Huber
> Date: Mon Oct 28 10:15:28 2019 +0100
>
> bsps/arm: Add support for small pages MMU
>
> The small page MMU support reduces the granularity for memory settings
> through the MMU from 1MiB sections to 4KiB small pages.
>
> Enable it by default on the realview_pbx_a9_qemu BSP.
>
> A BSP needs some minor changes to support it.
>
> --
> embedded brains GmbH
> Sebastian HUBER
> Dornierstr. 4
> 82178 Puchheim
> Germany
> email: sebastian.hu...@embedded-brains.de
> Phone: +49-89-18 94 741 - 16
> Fax: +49-89-18 94 741 - 08
> PGP: Public key available on request.
>
> embedded brains GmbH
> Registergericht: Amtsgericht München
> Registernummer: HRB 157899
> Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
> Unsere Datenschutzerklärung finden Sie hier: https://embedded-
> brains.de/datenschutzerklaerung/
>
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Re: Acessing PL devices of Xilinx Zedboard
Hello Jonathan, On 18/11/2020 17:00, Jonathan Brandmeyer wrote: Caveat: My information could be a little out of date. We're still running on a pre-release version of RTEMS 5.0. But hopefully this points you in the right direction. In particular, I know that some work has been done to support 4kB pages, but I don't know if the entry point arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache currently uses that support or not. the 4KiB pages MMU configuration was added with this commit: commit f9648baf65ecec2cd01c96557a677ad6ecc06b11 Author: Sebastian Huber Date: Mon Oct 28 10:15:28 2019 +0100 bsps/arm: Add support for small pages MMU The small page MMU support reduces the granularity for memory settings through the MMU from 1MiB sections to 4KiB small pages. Enable it by default on the realview_pbx_a9_qemu BSP. A BSP needs some minor changes to support it. -- embedded brains GmbH Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de Phone: +49-89-18 94 741 - 16 Fax: +49-89-18 94 741 - 08 PGP: Public key available on request. embedded brains GmbH Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
RE: Acessing PL devices of Xilinx Zedboard
Hi Jonathan, Thank you very much for the tip. I did overwrite the translation table with an additional entry and can now successfully access the device. Cheers, Jan From: Jonathan Brandmeyer Sent: Wednesday, November 18, 2020 5:01 PM To: Sommer, Jan Cc: RTEMS Subject: Re: Acessing PL devices of Xilinx Zedboard On Wed, Nov 18, 2020 at 8:37 AM mailto:jan.som...@dlr.de>> wrote: Hello, We try to use the xilinx_zynq_zedboard BSP with some devices synthesized to the PL, e.g. a Xilinx NS16550 Uart. If I try to access any of the AXI registers, I get a fatal error with a vector number 0x04 (undefined instruction). Accessing the same register address from within a Xilinx standalone hello-world program works as expected. Could it be that during the RTEMS startup some of the system initialization is reset so that accessing the PL devices fails? The default memory map does not provide access to any of the PL address range. You'll have to override the weak symbol zynq_setup_mmu_and_cache to provide your own memory map. The MMU code only supports 1 MB superpages at this time. Caveat: My information could be a little out of date. We're still running on a pre-release version of RTEMS 5.0. But hopefully this points you in the right direction. In particular, I know that some work has been done to support 4kB pages, but I don't know if the entry point arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache currently uses that support or not. -- Jonathan Brandmeyer PlanetiQ ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
Re: Acessing PL devices of Xilinx Zedboard
On Wed, Nov 18, 2020 at 8:37 AM wrote: > Hello, > > We try to use the xilinx_zynq_zedboard BSP with some devices synthesized > to the PL, e.g. a Xilinx NS16550 Uart. > If I try to access any of the AXI registers, I get a fatal error with a > vector number 0x04 (undefined instruction). > Accessing the same register address from within a Xilinx standalone > hello-world program works as expected. > Could it be that during the RTEMS startup some of the system > initialization is reset so that accessing the PL devices fails? > The default memory map does not provide access to any of the PL address range. You'll have to override the weak symbol zynq_setup_mmu_and_cache to provide your own memory map. The MMU code only supports 1 MB superpages at this time. Caveat: My information could be a little out of date. We're still running on a pre-release version of RTEMS 5.0. But hopefully this points you in the right direction. In particular, I know that some work has been done to support 4kB pages, but I don't know if the entry point arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache currently uses that support or not. -- Jonathan Brandmeyer PlanetiQ ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
Acessing PL devices of Xilinx Zedboard
Hello, We try to use the xilinx_zynq_zedboard BSP with some devices synthesized to the PL, e.g. a Xilinx NS16550 Uart. If I try to access any of the AXI registers, I get a fatal error with a vector number 0x04 (undefined instruction). Accessing the same register address from within a Xilinx standalone hello-world program works as expected. Could it be that during the RTEMS startup some of the system initialization is reset so that accessing the PL devices fails? I tried to boot the RTEMS application with u-boot and with the Xilinx Vitis IDE. At least the latter should initialize the PS correctly. Does someone have some suggestions where to look? Best regards, Jan Deutsches Zentrum für Luft- und Raumfahrt e. V. (DLR) German Aerospace Center Institute for Software Technology | Software for Space Systems and Interactive Visualization | Lilienthalplatz 7 | 38108 Braunschweig | Germany Jan Sommer ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
