Re: [USRP-users] Sample code for twin RX

Hello Snehasish: There are some example programs which illustrate these topics. https://github.com/EttusResearch/uhd/blob/maint/host/examples/rx_multi_samples.cpp https://github.com/EttusResearch/uhd/blob/maint/host/examples/tx_timed_samples.cpp

[USRP-users] State of local oscillators after "Late Command" error

Hi usrp-users, I am working on my handling of "Late Command" errors. In my case, this can occur due to timed tuned requests, or a timed receive or send. If there is a late command error on a send or recv, will the state of the transmit or receive LO change? I'm concerned about the relative

Re: [USRP-users] Flow control in UHD

Hi, RFNoC has flow control built in. By design, the host will not transmit a packet to your RFNoC block unless it can accept that packet. The flow control mechanism happens behind the scenes, there is nothing special you need to do. Jonathon On Tue, Aug 15, 2017 at 11:45 AM, James Dunn via

Re: [USRP-users] Building FPGA image

I've done it many times. When you open it and you do a save-as of the project, make sure that you don't check the option box to copy the files over, you want to leave them in their current location. On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote: Hi folks, Has

[USRP-users] Building FPGA image

Hi folks, Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design into Vivado 2015.4 and created the FPGA image using its graphical Interface? I am still unable to do so. I want to create a standard FPGA image using Vivado GUI. I have first run the command “make X310_RFNOC_HG

Re: [USRP-users] Uhd Python API rx and tx samples

Hi Ivan, I'm sorry, your question isn't very clear. You'll find all the documentation to the functions wrapped in python from our UHD manual on https://files.ettus.com/manual. Best regards, Marcus On 08/15/2017 08:49 PM, Ivan Zahartchuk via USRP-users wrote: > Hello.How to interrupt the

Re: [USRP-users] BasicTX daughterboard block diagram

Hi Ali, I'm a bit confused about the disconnect between your subject line and your question. The BasicTX is really just a transformer; see its schematic on https://files.ettus.com/schematics ; the schematic is so simple that we never cared to do a block diagram. The USRP1 (or: any device in

[USRP-users] USRP1 external clock modification

Hi all, I just want to increase the clock rate and have more stable one (less than 1 ppm). I read the manual and I know how I can change the crystal, but I would be grateful if you tell me what the maximum frequency is when I provide it externally (up to what frequency the DAC can work properly?)

[USRP-users] BasicTX daughterboard block diagram

hi all, I would like to know some more details about "BasicTX" daughterboards. Actually, I can't find out its 1~250 Mhz frequency range. I am using it in a USRP1, and I can't generate a frequency more than 64 MHz/ 2 which is 32 MHz ! ___ USRP-users

Re: [USRP-users] Receiver Sensitivity of NI USRP 2954R

Hello Snehasish, Here is the performance data for the UBX daughtercard and X3x0. The sensitivity changes with frequency and gain. http://files.ettus.com/performance_data/ubx/UBX-without-UHD-corrections.pdf Regards, Derek On Wed, Aug 16, 2017 at 8:14 AM, Snehasish Kar via USRP-users <

[USRP-users] Receiver Sensitivity of NI USRP 2954R

Hello What is the Receiver sensitivity of NI USRP 2954R? BR Snehasish ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com